Datasheet

–2–
AD7888–SPECIFICATIONS
(V
DD
= 2.7 V to 5.25 V, REFIN/REFOUT = 2.5 V External/Internal Reference unless
otherwise noted; f
SCLK
= 2 MHz (V
DD
= 2.7 V to 5.25 V); T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter A Version
1
B Version
1
Unit Test Condition/Comment
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
2, 3
(SNR) 71 71 dB typ f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
Total Harmonic Distortion
2
(THD) –80 –80 dB typ f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
Peak Harmonic or Spurious Noise
2
–80 –80 dB typ f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
Intermodulation Distortion
2
(IMD)
Second Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
Third Order Terms –78 –78 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
Channel-to-Channel Isolation
2
–80 –80 dB typ f
IN
= 25 kHz
Full Power Bandwidth 2.5 2.5 MHz typ @ 3 dB
DC ACCURACY Any Channel
Resolution 12 12 Bits
Integral Nonlinearity
2
± 2 ± 1 LSB max
Differential Nonlinearity
2
± 2 –1/+1.5 LSB max Guaranteed No Missed Codes to 11 Bits (A Grade)
Guaranteed No Missed Codes to 12 Bits (B Grade)
Offset Error ± 6 ± 6 LSB max V
DD
= 4.75 V to 5.25 V (Typically ± 3 LSB)
± 4.5 ± 4.5 LSB max V
DD
= 2.7 V to 3.6 V (Typically ± 2 LSB)
Offset Error Match
2
2 2 LSB typ
Gain Error
2
± 2 ± 2 LSB max Typically 30 LSB with Internal Reference
Gain Error Match
2
3 3 LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
REF
0 to V
REF
Volts
Leakage Current ± 1 ± 1 µA max
Input Capacitance 38 38 pF typ When in Track
4 4 pF typ When in Hold
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range 2.5/V
DD
2.5/V
DD
V min/max Functional from 1.2 V
Input Impedance 5 5 kΩ typ Very High Impedance If Internal Reference Disabled
REFOUT Output Voltage 2.45/2.55 2.45/2.55 V min/max
REFOUT Tempco ± 50 ± 50 ppm/°C typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 V min V
DD
= 4.75 V to 5.25 V
2.1 2.1 V min V
DD
= 2.7 V to 3.6 V
Input Low Voltage, V
INL
0.8 0.8 V max V
DD
= 2.7 V to 5.25 V
Input Current, I
IN
± 10 ± 10 µA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
4
10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
I
SOURCE
= 200 µA
V
DD
– 0.5 V
DD
– 0.5 V min V
DD
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 200 µA
Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance
5
10 10 pF max
Output Coding Straight (Natural) Binary
CONVERSION RATE
Throughput Time 16 16 SCLK Cycles Conversion Time + Acquisition Time. 125 kSPS with
2 MHz Clock
Track/Hold Acquisition Time
2
1.5 1.5 SCLK Cycles
Conversion Time 14.5 14.5 SCLK Cycles 7.25 µs (2 MHz Clock)
REV. C