Datasheet

AD7887
Rev. D | Page 5 of 24
TIMING SPECIFICATIONS
1
Table 2.
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description
f
SCLK
2
2 2 MHz max
t
CONVERT
14.5 × t
SCLK
14.5 × t
SCLK
t
ACQ
1.5 × t
SCLK
1.5 × t
SCLK
Throughput time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
t
1
10 10 ns min
CS
to SCLK setup time
t
2
3
30 60 ns max
Delay from CS
until DOUT three-state disabled
t
3
3
75 100 ns max Data access time after SCLK falling edge
t
4
20 20 ns min Data setup time prior to SCLK rising edge
t
5
20 20 ns min Data valid to SCLK hold time
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
8
4
80 80 ns max
CS
rising edge to DOUT high impedance
t
9
5 5 μs typ Power-up time from shutdown
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA I
OL
200µA I
OH
1.6V
TO
O
UTPUT
PIN
C
L
50pF
06191-002
Figure 2. Load Circuit for Digital Output Timing Specifications