Datasheet

REV. E
AD7884/AD7885
–7–
PIN FUNCTION DESCRIPTIONS
AD7884 AD7885 AD7885A Description
V
INV
V
INV
V
INV
This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied 3 V reference.
V
REF–
V
REF–
V
REF–
This is the negative reference input and can be obtained by using an external amplifier to
invert the positive reference input. In this case, the amplifier output is connected to V
REF–
.
See Figure 6.
± 3V
IN
S ± 3V
IN
SThis is the analog input sense pin for the ± 3 V analog input range on the AD7884 and
AD7885A.
± 3V
IN
F ± 3V
IN
FThis is the analog input force pin for the ± 3 V analog input range on the AD7884 and
AD7885A. When using this input range, the ± 5V
IN
F and ± 5V
IN
S pins should be tied to
AGND.
± 3V
IN
This is the analog input pin for the ± 3 V analog input range on the AD7885. When using
this input range, the ±5V
IN
F and ± 5V
IN
S pins should be tied to AGND.
± 5V
IN
S ± 5V
IN
S ± 5V
IN
S This is the analog input sense pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A.
± 5V
IN
F ± 5V
IN
F ± 5V
IN
F This is the analog input force pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A. When using this input range, the ± 3V
IN
F and ± 3V
IN
S pins should be tied
to AGND.
AGNDS AGNDS AGNDS This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
AGNDF AGNDF AGNDF This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
AV
DD
AV
DD
AV
DD
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
AV
SS
AV
SS
AV
SS
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
GND GND GND This is the ground return for the sample-and-hold section.
V
SS
V
SS
V
SS
Negative Supply for the 9-Bit ADC
V
DD
V
DD
V
DD
Positive Supply for the 9-Bit ADC and All Device Logic
CONVST CONVST CONVST This asynchronous control input starts conversion.
CS CS CS Chip Select Control Input
RD RD RD Read Control Input. This is used in conjunction with CS to read the conversion result
from the device output latch.
HBEN HBEN High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
BUSY BUSY BUSY Busy Output. The BUSY output goes low when the conversion begins and stays low until
it is completed, at which time it goes high.
DB0–DB15 16-Bit Parallel Data-Word Output on the AD7884
DB0–DB7 DB0–DB7 8-Bit Parallel Data Byte Output on the AD7885
DGND DGND DGND Ground Return for All Device Logic
V
REF+
FV
REF+
FV
REF+
FReference Force Input
V
REF+
SV
REF+
SV
REF+
SReference Sense Input. The device operates from a 3 V reference.