Datasheet

REV. D
–3–
AD7884/AD7885
TIMING CHARACTERISTICS
1
Limit at 25ⴗC Limit at T
MIN
, T
MAX
Parameter (All Versions) (A, B, and J Versions) Unit Conditions/Comments
t
1
50 50 ns min CONVST Pulsewidth
t
2
100 100 ns max CONVST to BUSY Low Delay
t
3
00 ns min CS to RD Setup Time
t
4
60 60 ns min RD Pulsewidth
t
5
00 ns min CS to RD Hold Time
t
6
2
57 57 ns max Data Access Time after RD
t
7
3
55 ns min Bus Relinquish Time after RD
50 50 ns max
t
8
40 40 ns min New Data Valid before Rising Edge of BUSY
t
9
10 80 ns min HBEN to RD Setup Time
t
10
25 25 ns min HBEN to RD Hold Time
t
11
60 60 ns min HBEN Low Pulse Duration
t
12
60 60 ns min HBEN High Pulse Duration
t
13
55 70 ns max Propagation Delay from HBEN Falling to Data Valid
t
14
55 70 ns max Propagation Delay from HBEN Rising to Data Valid
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
6
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
7
, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
DD
= +5 V ⴞ 5%, V
SS
= –5 V ⴞ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)
TO OUTPUT PIN
2.1V
C
L
100pF
200␮A
I
OH
1.6mA
I
OL
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time