Datasheet

AD7880
REV. 0
–5–
+
–
R
V
INA
V
INB
R
V
DAC
Figure 4. AD7880 Input Circuit
The AD7880 accommodates three separate input ranges, 0 to
V
REF
, 0 to 2 V
REF
and ±V
REF
. The input configurations corre-
sponding to these ranges are shown in Figures 5, 6 and 7.
With V
REF
= V
DD
and using a nominal V
DD
of +5 V, the input
ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in
Table II.
Table II. Analog Input Ranges
Analog Input
Input Connections
Connection
Range V
REF
V
INA
V
INB
Diagram
0 V to +5 V V
DD
V
IN
V
IN
Figure 5
0 V to +10 V V
DD
V
IN
AGND Figure 6
±5 V V
DD
V
IN
V
REF
Figure 7
+
–
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= 0 TO V
REF
V
IN
Figure 5. 0 to V
REF
Unipolar Input Configuration
+
–
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= 0 TO 2V
REF
V
IN
Figure 6. 0 to 2 V
REF
Unipolar Input Configuration
+
–
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= V
REF
V
IN
±
Figure 7. ± V
REF
Bipolar Input Configuration
CIRCUIT INFORMATION
The AD7880 is a +5 V single supply 12-bit A/D converter. The
part requires no external components apart from a 2.5 MHz ex-
ternal clock and power supply decoupling capacitors. It contains
a 12-bit successive approximation ADC based on a fast-settling
voltage-output DAC, a high speed comparator and SAR, as well
as the necessary control logic. The charge balancing comparator
used in the AD7880 provides the user with an inherent track-
and-hold function. The ADC is specified to work with sampling
rates up to 66 kHz.
CONVERTER DETAILS
The AD7880 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. The rising edge of the
CONVST pulse places the track/hold
amplifier into “HOLD” mode. The conversion cycle then takes
between 26 and 28 clock periods. The maximum specified con-
version time is 12 µs. This corresponds to a conversion cycle
time of 28 clock periods with a CLKIN frequency of 2.5 MHz
and also includes internal propagation delays. During conver-
sion the
BUSY output will remain low, and the output databus
drivers will be three-stated. When a conversion is completed,
the
BUSY output will go to a high level, and the result of the
conversion can be read by bringing
CS and RD low.
The track/hold amplifier acquires a 12-bit input signal in 3µs.
The overall throughput time for the AD7880 is equal to the
conversion time plus the track/hold acquisition time. For a
2.5 MHz input clock the throughput time is 15 µs.
REFERENCE INPUT
For specified performance, it is recommended that the reference
input be tied to V
DD
. The part, however, will operate with a ref-
erence down to 2.5 V though with reduced performance specifi-
cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
versus V
REF
.
V
REF
must not be allowed to go above V
DD
by more than
100 mV.
74
72
70
68
66
64
62
60
2345
V
REF
– Volts
SNR
– dBs
F = 51.2kHz
S
F = 2.525kHz
IN
T = 25 C
A
Figure 3. SNR vs. V
REF
ANALOG INPUT
The AD7880 has two analog input pins, V
INA
and V
INB
. Figure
4 shows the input circuitry to the ADC sampling comparator.
The on-board attenuator network, made up of equal resistors,
allows for various input ranges.