Datasheet
AD7879/AD7889
Rev. C | Page 33 of 40
DIN
CW
15
CW
14
CW
13
CW
8
CW
1
CW
0
D15 D14
SCL
CW
12
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
D1 D0D1 D0
D15
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D15D14
1
32
2 3 4
15 16 17 18 31 3433 4847 49
CS
CW
11
CW
10
CW
9
CW
7
CW
2
CW
6
CW
5
CW
4
CW
3
11 12 13 14
5 6 7 8 9 10
16-BIT COMMAND WORD
ENABLE WORD
R/W STARTING REGISTER ADDRESS
07667-039
Figure 40. Sequential Register Write, SPI Timing
NOTES
1. DATA BITS ARE LATCHED ON SCL RISING EDGES. SCL CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE DOUT PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
CW
11
CW
10
CW
13
CW
12
DIN
CW
15
CW
14
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
X X X
CW
8
16-BIT READBACK DATA
5 326 7 8 9 10 11 12 13 14 15 16 30 31
SCL
1 2 3 4
X X X
17 18 19
CS
XXX XXXXXX XXX
DOUT
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
D2 D1 D0
XXX
D15 D14 D13
XXX
16-BIT COMMAND WORD
ENABLE WORD R/W REGISTER ADDRESS
t
4
t
5
t
1
t
3
t
2
t
6
t
7
t
8
07667-040
Figure 41. Single Register Readback, SPI Timing
Reading Data
A read transaction begins when the master writes the command
word to the AD7879/AD7889 with the read/write bit set to 1. The
master then supplies 16 clock pulses per data-word to be read,
and the AD7879/AD7889 clock out data from the addressed
register on the DOUT line. The first data-word is clocked out
on the first falling edge of SCL following the command word,
as shown in Figure 41.
The AD7879/AD7889 continue to clock out data on the DOUT
line provided that the master continues to supply the clock signal
on SCL. The read transaction ends when the master takes
CS
high.
If the AD7879/AD7889 address pointer reaches its maximum
value, the AD7879/AD7889 repeatedly clock out data from the
addressed register. The address pointer does not wrap.