Datasheet

AD7879/AD7889
Rev. C | Page 29 of 40
TEMP
MASK
AUX/
VBAT
MASK
INT
MODE
GPIO
ALERT
AUX/
VBAT
LOW
AUX/
VBAT
HIGH
TEMP
HIGH
X+ Y+ Z1 Z2 AUX VBAT TEMP
NOT
USED
07667-031
015
TEMP
LOW
Figure 32. Control Register 3
CONTROL REGISTER 3
Control Register 3 (Address 0x03) includes the interrupt
register (Bits[15:8]) and the sequencer bits (Bits[7:0]).
Sequencer (Control Register 3, Bits[7:0])
The sequencer bits control which channels are converted during
a conversion sequence in both slave mode and master mode.
To include a measurement in a sequence, the relevant bit must
be set in the sequence. Setting Bit 7 includes a measurement on
the X+ channel (Y position). Setting Bit 6 includes a measure-
ment on the Y+ channel (X position), and so on (see Table 14).
Figure 32 illustrates the correspondence between the bits in
Control Register 3 and the various measurements. Bit 0 is
not used.
SLAVE MODE
CONVERSION
SEQUENCE
TIMER = 00?
ST
ART TIMER
WA
IT FOR TIMER
SINGLE
CONVERSION
MASTER MODE
WAIT FOR
FIRST TOUCH
CONVERSION
SEQUENCE
SCREEN
TOUCHED?
TIMER = 00?
START TIMER
WAIT FOR TIMER
SCREEN
TOUCHED?
IDLE
ADC MODE?
10
YES
YES
YES
NO
NO
YES
NO
NO
11
00
07667-032
01
Figure 33. Conversion Modes
FCD
REQ’D?
WAIT FOR
ACQUISITION
ACQ
SET CHANNEL
CONVERT DATA
AVERAGE DATA
TRANSFER DATA
TO REGISTERS
SET ALERT AND
INTERRUPT
1
MEDIAN # MEANS MEDIAN
FILTER SIZE.
RANK NEW
DATA
(WAIT t
SORT
)
MEDIAN
# OF SAMPLES
TAKEN?
1
NO
YES
07667-033
START OF
CONVERSION
SEQUENCE
FCD
FCD
MAV FILTER
ENABLED
?
OUT-OF-
LIMIT?
END OF
SEQUENCE
?
YES
YES
YES
NO
NO
NO
YES
NO
Figure 34. Conversion Sequence