Datasheet

Data Sheet AD7877
Rev. D | Page 5 of 44
TIMING SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, unless otherwise noted, V
CC
= 2.7 V to 5.25 V, V
REF
= 2.5 V. Sample tested at 25°C to ensure compliance. All input
signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
DCLK
1
10 kHz min
20 MHz max
t
1
16 ns min
CS falling edge to first DCLK rising edge
t
2
20 ns min DCLK high pulse width
t
3
20
ns min
DCLK low pulse width
t
4
12 ns min DIN setup time
t
5
12 ns min DIN hold time
t
6
2
16 ns max
CS falling edge to DOUT, three-state disabled
t
7
2
16 ns max DCLK falling edge to DOUT valid
t
8
3
16 ns max
CS rising edge to DOUT high impedance
t
9
0
ns min
CS rising edge to DCLK ignored
1
Mark/space ratio for the DCLK input is 40/60 to 60/40.
2
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V.
3
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
TIMING DIAGRAMS
03796-004
DCLK
t
1
t
2
t
3
t
5
t
4
t
6
t
7
t
9
t
8
DIN
MSB LSB
MSB LSB
DOUT
1 2 3 15 16
CS
Figure 2. Detailed Timing Diagram
03796-003
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 3. Load Circuit for Digital Output Timing Specifications