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Data Sheet AD7877
Rev. D | Page 37 of 44
Register Name: Alert Status/Enable Register
Write Address: 0011
Read Address: 00011
Default Value: 0x000
Type: Read/write
Table 18.
Bit Name Read/Write Description
0 AUX1LO R/W When this bit is 1, the AUX1 channel is below its low limit
1 BAT1LO R/W When this bit is 1, the BAT1 channel is below its low limit
2 BAT2LO R/W When this bit is 1, the BAT2 channel is below its low limit
3 TEMP1LO R/W When this bit is 1, the TEMP1 channel is above its low limit
4 AUX1HI R/W When this bit is 1, the AUX1 channel is above its high limit
5 BAT1HI R/W When this bit is 1, the BAT1 channel is above its high limit
6 BAT2HI R/W When this bit is 1, the BAT2 channel is above its high limit
7 TEMP1HI R/W When this bit is 1, the TEMP1 channel is below its high limit
8 AUX1EN R/W
Setting this bit enables AUX1 as an interrupt source to the
ALERT output
9 BAT1EN R/W
Setting this bit enables BAT1 as an interrupt source to the
ALERT output
10 BAT2EN R/W
Setting this bit enables BAT2 as an interrupt source to the
ALERT output
11 TEMP1EN R/W
Setting this bit enables TEMP1 as an interrupt source to the
ALERT output
Register Name: AUX1 High Limit
Write Address: 0100
Read Address: 00100
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for Auxiliary Input 1.
Register Name: AUX1 Low Limit
Write Address: 0101
Read Address: 00101
Default Value: 0x000
Type: Read/write
This register contains the 12-bit low limit for Auxiliary Input 1.
Register Name: BAT1 High Limit
Write Address: 0110
Read Address: 00110
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for Battery
Monitoring Input 1.
Register Name: BAT1 Low Limit
Write Address: 0111
Read Address: 00111
Default Value: 0x000
Type: Read/write
This register contains the 12-bit low limit for Battery
Monitoring Input 1.
Register Name: BAT2 High Limit
Write Address: 1000
Read Address: 01000
Default Value: 0x000
Type: Read/write
This register contains the 12-bit high limit for Battery
Monitoring Input 2.