Datasheet

Data Sheet AD7873
Rev. F | Page 5 of 28
TIMING SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, unless otherwise noted; V
CC
= 2.7 V to 5.25 V, V
REF
= 2.5 V.
Table 2. Timing Specifications
1
Parameter Limit at T
MIN
, T
MAX
Unit Description
f
DCLK
2
10 kHz min
2 MHz max
t
ACQ
1.5 µs min Acquisition time
t
1
10 ns min
CS falling edge to first DCLK rising edge
t
2
60 ns max
CS falling edge to busy three-state disabled
t
3
3
60 ns max
CS falling edge to DOUT three-state disabled
t
4
200 ns min DCLK high pulse width
t
5
200 ns min DCLK low pulse width
t
6
60 ns max DCLK falling edge to BUSY rising edge
t
7
10 ns min Data setup time prior to DCLK rising edge
t
8
10 ns min Data valid to DCLK hold time
t
9
3
200 ns max Data access time after DCLK falling edge
t
10
0 ns min
CS rising edge to DCLK ignored
t
11
100 ns max
CS rising edge to BUSY high impedance
t
12
4
100 ns max
CS rising edge to DOUT high impedance
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the DCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4
t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Figure 2. Load Circuit for Digital Output Timing Specifications
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
02164-002