Datasheet
AD7870/AD7875/AD7876
Rev. C | Page 8 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RD
1
BUSY/INT
2
CLK
3
DB11/HBEN
4
CS
24
CONVST
23
12/8/CLK
22
V
SS
21
DB10/SSTRB
5
DB9/SCLK
6
DB8/SDATA
7
V
IN
20
REF OUT
19
AGND
18
DB7/LOW
8
V
DD
17
DB6/LOW
9
DB0/DB8
16
DB5/LOW
10
DB1/DB9
15
DB4/LOW
11
DB2/DB10
14
DGND
12
DB3/DB11
13
AD7870/
AD7875/
AD7876
TOP VIEW
(Not to Scale)
07730-004
Figure 2. DIP and SOIC Pin Configuration
1282726234
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC = NO CONNECT
DB11/HBEN
DB10/SSTRB
DB9/SCLK
NC
DB8/SDATA
DB7/LOW
DB6/LOW
V
SS
V
IN
REF OUT
NC
AGND
V
DD
DB0/DB8
CLK
BUSY/INT
RD
NC
CS
CONVST
12/8/CLK
DB5/LOW
DB4/LOW
DGND
NC
DB3/DB11
DB2/DB10
DB1/DB9
PIN 1
INDENTFIER
12 13 14 15 16 17 18
07730-005
AD7870/AD7875/
AD7876
TOP VIEW
(Not to Scale)
Figure 3. PLCC Pin Configuration
Table 5. Pin Function Descriptions
DIP and SOIC
Pin No.
PLCC
Pin No. Mnemonic Function
N/A 1, 8, 15,
22
NC No Connect.
1 2
RD
Read. Active low logic input. This input is used in conjunction with
CS
low to enable the data outputs.
2 3
BUSY
/
INT
Busy/Interrupt. Active low logic output indicating converter status. See Figure 14, Figure 15, Figure 16,
and Figure 17.
3 4 CLK
Clock Input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying this
pin to V
SS
enables the internal laser-trimmed clock oscillator.
4 5 DB11/HBEN
Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 12/
8
/CLK
input. When 12-bit parallel data is selected, this pin provides the DB11 output. When byte data is
selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is
low, DB7/LOW to DB0/DB8 become DB7 to DB0. With HBEN high, DB7/LOW to DB0/DB8 are used for
the upper byte of data (see ). Table 6
5 6
DB10/
SSTRB
Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output.
SSTRB
is an active low open-drain output that provides a strobe or framing pulse for serial data. An
external 4.7 kΩ pull-up resistor is required on
SSTRB
.
6 7 DB9/SCLK
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is
the gated serial clock output derived from the internal or external ADC clock. If the 12/
8
/CLK input is at
−5 V, then SCLK runs continuously. If 12/
8
/CLK is at 0 V, then SCLK is gated off after serial transmission is
complete. SCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.
7 9 DB8/SDATA
Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA is
an open-drain serial data output which is used with SCLK and
SSTRB
for serial data transfer. Serial data
is valid on the falling edge of SCLK while
SSTRB
is low. An external 4.7 kΩ pull-up resistor is required on
SDATA.
8 to11 10 to 13 DB7/LOW–
DB4/LOW
Three-state data outputs controlled by
CS
and
RD
. Their function depends on the 12/
8
/CLK and HBEN
inputs. With 12/
8
/CLK high, they are always DB7–DB4. With 12/
8
/CLK low or −5 V, their function is
controlled by HBEN (see ). Table 6
12 14 DGND Digital Ground. Ground reference for digital circuitry.
13 to 16 16 to 19 DB3/DB11–
DB0/DB8
Three-state data outputs which are controlled by
CS
and
RD
. Their function depends on the 12/
8
/CLK
and HBEN inputs. With 12/
8
/CLK high, they are always DB3–DB0. With 12/
8
/CLK low or −5 V, their
function is controlled by HBEN (see ). Table 6
17 20 V
DD
Positive Supply, +5 V ± 5%.