Datasheet
AD7870/AD7875/AD7876
Rev. C | Page 6 of 28
TIMING CHARACTERISTICS
V
DD
= +5 V ± 5%, V
SS
= −5 V ± 5%, AGND = DGND = 0 V. See Figure 14, Figure 15, Figure 16, and Figure 17. Timing specifications are
sample tested at 25°C to ensure compliance, unless otherwise noted. All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V)
and timed from a voltage level of 1.6 V.
Table 3.
Parameter
1
Limit at T
MIN
, T
MAX
(J, K, L, A, B, C Versions)
Limit at T
MIN
, T
MAX
(T Version) Units Conditions/Comments
t
1
50 50 ns min
CONVST
pulse width
t
2
0 0 ns min
CS
to RD setup time (Mode 1)
t
3
2
60 75 ns min
RD
pulse width
t
4
0 0 ns min
CS
to RD hold time (Mode 1)
t
5
70 70
ns max
RD
to INT delay
t
6
2, 3
57 70 ns max
Data access time after RD
t
7
2,
4
5 5 ns min
Bus relinquish time after RD
50 50
ns max
t
8
0 0 ns min
HBEN to RD setup time
t
9
0 0 ns min
HBEN to RD
hold time
t
10
100 100 ns min
SSTRB
to SCLK falling edge setup time
t
11
5
370 370 ns min SCLK cycle time
t
12
6
135 150 ns max SCLK to valid data delay. C
L
= 35 pF
t
13
20 20 ns min
SCLK rising edge to SSTRB
100 100 ns max
t
14
10 10 ns min Bus relinquish time after SCLK
100 100 ns max
t
15
60 60 ns min
CS
to RD setup time (Mode 2)
t
16
120 120
ns max
CS
to BUSY propagation delay
t
17
200 200 ns min
Data setup time prior to BUSY
t
18
0 0 ns min
CS
to RD hold time (Mode 2)
t
19
0 0 ns min
HBEN to CS
setup time
t
20
0 0 ns min
HBEN to CS
hold time
1
Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and
SSTRB
and a 2 kΩ pull-up on SCLK. The capacitance on all three outputs is 35 pF.
2
Timing specifications for t
3
, t
6
, and for the maximum limit at t
7
are 100% production tested.
3
t
6
is measured with the load circuits of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t
7
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 5.
5
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6
SDATA will drive higher capacitive loads but this will add to t
12
since it increases the external RC time constant (4.7 kΩ||C
L
) and thus the time to reach 2.4 V.