Datasheet

–2–
AD7869–SPECIFICATIONS
ADC SECTION
(V
DD
= +5 V 6 5%, V
SS
= –5 V 6 5%, AGND = DGND = 0 V, f
CLK
= 2.0 MHz external.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter J Version
1
A Version
1
Units Test Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio
3, 4
(SNR) @ +25°C 78 78 dB min V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 83 kHz
T
MIN
to T
MAX
78 77 dB min
Total Harmonic Distortion (THD) –86 –86 dB typ V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 83 kHz
Peak Harmonic or Spurious Noise –86 –86 dB typ V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 83 kHz
Intermodulation Distortion (IMD)
Second Order Terms –86 –86 dB typ fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
Third Order Terms –88 –88 dB typ fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
Track/Hold Acquisition Time 2 2 µs max
DC ACCURACY
Resolution 14 14 Bits
Minimum Resolution 14 14 Bits No Missing Codes Are Guaranteed
Integral Nonlinearity ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max
Bipolar Zero Error ±20 ±20 LSB max
Positive Gain Error
5
±20 ±20 LSB max
Negative Gain Error
5
±20 ±20 LSB max
ANALOG INPUT
Input Voltage Range ±3 ±3 Volts
Input Current ±1 ±1 mA max
REFERENCE OUTPUT
6
RO ADC @ +25°C 2.99/3.01 2.99/3.01 V min/ V max
RO ADC TC ±25 ±25 ppm/°C typ
±40 ±ppm/°C max
Reference Load Sensitivity
(∆RO ADC vs. ∆I) –1.5 –1.5 mV max Reference Load Current Change (0–500 µA),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS
(
CONVST, CLK, CONTROL)
Input High Voltage, V
INH
2.4 2.4 V min V
DD
= 5 V ± 5%
Input Low Voltage, V
INL
0.8 0.8 V max V
DD
= 5 V ± 5%
Input Current, I
IN
±10 ±10 µA max V
IN
= 0 V to V
DD
Input Current
7
(CONTROL & CLK) ±10 ±10 µA max V
IN
= V
SS
to DGND
Input Capacitance, C
IN
8
10 10 pF max
LOGIC OUTPUTS
DR,
RFS Outputs
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 1.6 mA, Pull-Up Resistor = 4.7 kΩ
RCLK Output
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 2.6 mA, Pull-Up Resistor = 2 kΩ
DR,
RFS, RCLK Outputs
Floating-State Leakage Current ±10 ±10 µA max
Floating-State Output Capacitance
8
15 15 pF max
CONVERSION TIME
External Clock 10 10 µs max
Internal Clock 10 10 µs max The Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENTS For Both DAC and ADC
V
DD
+5 +5 V nom ±5% for Specified Performance
V
SS
–5 –5 V nom ±5% for Specified Performance
I
DD
22 22 mA max Cumulative Current from the Two V
DD
Pins
I
SS
12 12 mA max Cumulative Current from the Two V
SS
Pins
Total Power Dissipation 170 170 mW max Typically 130 mW
NOTES
1
Temperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.
2
V
IN
= ±3 V.
3
SNR calculation includes distortion and noise components.
4
SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5
Measured with respect to internal reference.
6
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
7
Tying the CONTROL input to V
DD
places the device in a factory test mode where normal operation is not exhibited.
8
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B