Datasheet

REV. B
AD7865
–4–
TIMING CHARACTERISTICS
1, 2
Parameter A, B, Y Versions Unit Test Conditions/Comments
t
CONV
2.4 µs max Conversion Time, Internal Clock
3.2 µs max Conversion Time, External Clock (5 MHz)
t
ACQ
0.35 µs max Acquisition Time
t
BUSY
No. of Channels Selected Number of Channels Multiplied by t
CONV
× (t
CONV
) µs max
t
WAKE-UP
—External V
REF
3
1 µs max STBY Rising Edge to CONVST Rising Edge
t
1
35 ns min CONVST Pulsewidth
t
2
70 ns min CONVST Rising Edge to BUSY Rising Edge
Read Operation
t
3
0 ns min CS to RD Setup Time
t
4
0 ns min CS to RD Hold Time
t
5
35 ns min Read Pulsewidth
t
6
4
35 ns max Data Access Time after Falling Edge of RD, V
DRIVE
= 5 V
40 ns max Data Access Time after Falling Edge of RD, V
DRIVE
= 3 V
t
7
5
5 ns min Bus Relinquish Time after Rising Edge of RD
30 ns max
t
8
15 ns min Time Between Consecutive Reads
t
9
120 ns min EOC Pulsewidth
180 ns max
t
10
70 ns max RD Rising Edge to FRSTDATA Edge (Rising or Falling)
t
11
15 ns max EOC Falling Edge to FRSTDATA Falling Delay
t
12
0 ns min EOC to RD Delay
Write Operation
t
13
20 ns min WR Pulsewidth
t
14
0 ns min CS to WR Setup Time
t
15
0 ns min WR to CS Hold Time
t
16
5 ns min Input Data Setup Time of Rising Edge of WR
t
17
5 ns min Input Data Hold Time
External Clock
t
18
200 ns min CONVST Falling Edge to CLK Rising Edge
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 6, 7 and 8.
3
Refer to the Standby Mode Operation section. The MAX specification of 1 µs is valid when using a 0.1 µF decoupling capacitor on the V
REF
pin.
4
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
50pF
TO OUTPUT
PIN
1.6V
400A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(V
DD
= 5 V  5%, AGND = DGND = 0 V, V
REF
= Internal, Clock = Internal; all specifications
T
MIN
to T
MAX
unless otherwise noted.)