Datasheet

AD7864
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
V
DRIVE
= 5 V± 5%, AGND = DGND = 0 V, V
REF
= internal, clock = internal; all specifications T
MIN
to T
MAX
, unless otherwise noted.
1, 2
Table 2.
Parameter A, B Versions Unit Test Conditions/Comments
t
CONV
1.65 μs max Conversion time, internal clock
13 Clock cycles Conversion time, external clock
2.6 μs max CLKIN = 5 MHz
t
ACQ
0.34 μs max Acquisition time
t
BUSY
No. of channels ×
(t
CONV
+ t
9
) − t
9
μs max
Selected number of channels multiplied by (t
CONV
+
EOC
pulse
width)—
EOC
pulse width
t
WAKE-UP
—External V
REF
2 μs max
STBY
rising edge to
CONVST
rising edge
t
WAKE-UP
—Internal V
REF
3
6 ms max
STBY
rising edge to
CONVST
rising edge
t
1
35 ns min
CONVST
pulse width
t
2
70 ns max
CONVST
rising edge to BUSY rising edge
READ OPERATION
t
3
0 ns min
CS
to
RD
setup time
t
4
0 ns min
CS
to
RD
hold time
t
5
35 ns min Read pulse width, V
DRIVE
= 5 V
40 ns min Read pulse width, V
DRIVE
= 3 V
t
6
4
35 ns max
Data access time after falling edge of
RD
, V
DRIVE
= 5 V
40 ns max
Data access time after falling edge of
RD
, V
DRIVE
= 3 V
t
7
5
5 ns min
Bus relinquish time after rising edge of
RD
30 ns max
t
8
10 ns min Time between consecutive reads
t
9
75 ns min
EOC
pulse width
180 ns max
t
10
70 ns max
RD
rising edge to FRSTDATA edge (rising or falling)
t
11
15 ns max
EOC
falling edge to FRSTDATA falling delay
t
12
0 ns min
EOC
to
RD
delay
WRITE OPERATION
t
13
20 ns min
WR
pulse width
t
14
0 ns min
CS
to
WR
setup time
t
15
0 ns min
WR
to
CS
hold time
t
16
5 ns min
Input data setup time of rising edge of
WR
t
17
5 ns min Input data hold time
1
Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 9, Figure 10,and Figure 11.
3
Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 μF decoupling capacitor on the V
REF
pin.
4
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is
then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part, and as such, are independent of external bus loading capacitances.
TO
O
UTPUT
50pF
1.6V
400µA
1.6mA
01341-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time