Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal MQFP 44

4-Channel, Simultaneous Sampling,

High Speed, 12-Bit ADC

AD7864

Rev. D

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FEATURES

High speed (1.65 μs) 12-bit ADC

4 simultaneously sampled inputs

4 track-and-hold amplifiers

0.35 μs track-and-hold acquisition time

1.65 μs conversion time per channel

HW/SW select of channel sequence for conversion

Single-supply operation

Selection of input ranges

±10 V, ±5 V for AD7864-1

±2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2

High speed parallel interface that allows

Interfacing to 3 V processors

Low power, 90 mW typical

Power saving mode, 20 μW typical

Overvoltage protection on analog inputs

APPLICATIONS

AC motor control

Uninterrupted power supplies

Data acquisition systems

Communications

GENERAL DESCRIPTION

The AD7864 is a high speed, low power, 4-channel, simulta-

neous sampling 12-bit analog-to-digital converter (ADC) that

operates from a single 5 V supply. The part contains a 1.65 μs

successive approximation ADC, four track-and-hold amplifiers,

a 2.5 V reference, an on-chip clock oscillator, signal conditioning

circuitry, and a high speed parallel interface. The input signals

on four channels sample simultaneously preserving the relative

phase information of the signals on the four analog inputs. The

part accepts analog input ranges of ±10 V, ±5 V (AD7864-1), 0 V

to +2.5 V, 0 V to +5 V (AD7864-2), and ±2.5 V (AD7864-3).

Any subset of the four channels can be converted to maximize

the throughput rate on the selected sequence. Select the channels to

convert via hardware (channel select input pins) or software (pro-

gramming the channel select register).

A single conversion start signal (

CONVST

) simultaneously places

all the track-and-holds into hold and initiates a conversion se-

quence for the selected channels. The

EOC

signal indicates the end

of each individual conversion in the selected conversion sequence.

The BUSY signal indicates the end of the conversion sequence.

FUNCTIONAL BLOCK DIAGRAM

STBY

FRSTDATA

INT/EXT CLOCK

SELECT

OUTPUT

DATA

REGISTERS

2.5V

REFERENCE

SIGNAL

SCALING

IN1A

IN1B

IN2A

IN2B

IN3A

IN3B

IN4A

IN4B

BUSY

SIGNAL

SCALING

SIGNAL

SCALING

SIGNAL

SCALING

TRACK-AND-HOLD

×4

EOC

DB0

DB11

AGND

DGND

DRIVE

REF

GNDV

REF

6kΩ

AD7864

12-BIT

ADC

SOFTWARE

LATCH

CONVERSION

CONTROL LOGIC

MUX

CONVST

SL2SL1 SL3 SL4

H/S

SEL

CLKIN

INT/EXT

CLK

AGND AGND

INT

CLOCK

DB0 TO DB3

01341-001

Figure 1.

Data is read from the part by a 12-bit parallel data bus using the

standard

and

signals. Maximum throughput for a single

channel is 500 kSPS. For all four channels, the maximum throughput

is 130 kSPS for the read-during-conversion sequence operation.

The throughput rate for the read-after-conversion sequence

operation depends on the read cycle time of the processor. See

the section. The AD7864 is available in a

small (0.3 square inch area) 44-lead MQFP.

Timing and Control

PRODUCT HIGHLIGHTS

1. Four track-and-hold amplifiers and a fast (1.65 μs) ADC for

simultaneous sampling and conversion of any subset of the

four channels.

2. A single 5 V supply consuming only 90 mW typical, makes

it ideal for low power and portable applications. See the

Standby Mode Operation section.

3. High speed parallel interface for easy connection to micro-

processors, microcontrollers, and digital signal processors.

4. Available in three versions with different analog input

ranges. The AD7864-1 offers the standard industrial input

ranges of ±10 V and ±5 V; the AD7864-3 offers the common

signal processing input range of ±2.5 V; the AD7864-2 can

be used in unipolar, 0 V to 2.5 V and 0 V to 5 V,

applications.

5. Features very tight aperture delay matching between the

four input sample-and-hold amplifiers.

Summary of content (28 pages)

PAGE 1
4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC AD7864 High speed (1.65 μs) 12-bit ADC 4 simultaneously sampled inputs 4 track-and-hold amplifiers 0.35 μs track-and-hold acquisition time 1.65 μs conversion time per channel HW/SW select of channel sequence for conversion Single-supply operation Selection of input ranges ±10 V, ±5 V for AD7864-1 ±2.5 V for AD7864-3 0 V to 2.
PAGE 2
AD7864 TABLE OF CONTENTS Features .............................................................................................. 1 Standby Mode Operation .......................................................... 18 Applications ....................................................................................... 1 Accessing the Output Data Registers....................................... 18 General Description .........................................................................
PAGE 3
AD7864 SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter SAMPLE AND HOLD −3 dB Full Power Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching A Version 1 B Version Unit 3 20 50 4 3 20 50 4 MHz typ ns max ps max ns max fIN = 100.
PAGE 4
AD7864 Parameter AD7864-2 Input Voltage Range Input Current (0 V to 2.
PAGE 5
AD7864 TIMING CHARACTERISTICS VDRIVE = 5 V± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted. 1, 2 Table 2. Parameter tCONV tACQ tBUSY A, B Versions 1.65 13 2.6 0.34 No.
PAGE 6
AD7864 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3.
PAGE 7
AD7864 DB6 DVDD VDRIVE DGND DB5 DB4 DB3 DB2 DB1 DB0 EOC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 DB7 BUSY 1 PIN 1 FRSTDATA 2 32 DB8 CONVST 3 31 DB9 CS 4 30 DB10 29 DB11 RD 5 AD7864 WR 6 TOP VIEW (Not to Scale) SL1 7 28 CLKIN 27 INT/EXT CLK SL2 8 26 AGND SL3 9 25 AVDD SL4 10 24 VREF 23 VREF GND H/S SEL 11 01341-003 STBY VIN1A VIN1B VIN2A VIN2B AGND VIN3A VIN3B VIN4A VIN4B AGND 12 13 14 15 16 17 18 19 20 21 22 Figure 3.
PAGE 8
AD7864 Pin No. 27 INT/EXT CLK Mnemonic 28 CLKIN 29 to 34 DB11 to DB6 35 DVDD 36 VDRIVE 37 DGND 38, 39 40 to 43 DB5, DB4 DB3 to DB0 44 EOC Description Internal/External Clock Select Input. When this pin is at Logic 0, the AD7864 uses its internally generated master clock. When this pin is at Logic 1, the master clock is generated externally to the device. Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864.
PAGE 9
AD7864 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
PAGE 10
AD7864 It means that the user must wait for the duration of the trackand-hold acquisition time after the end of conversion or after a step input change to VINxA/VINxB before starting another conversion to ensure that the part operates to specification. Rev.
PAGE 11
AD7864 THEORY OF OPERATION CONVERTER DETAILS The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit ADC that operates from a single 5 V supply. The part contains a 1.65 μs successive approximation ADC, four track-and-hold amplifiers, an internal 2.5 V reference, and a high speed parallel interface. There are four analog inputs that can be simultaneously sampled, thus preserving the relative phase information of the signals on all four analog inputs.
PAGE 12
AD7864 nominal source impedance for this output. The tolerance on the internal reference is ±10 mV at 25°C with a typical temperature coefficient of 25 ppm/°C and a maximum error overtemperature of ±20 mV. If the application requires a reference with a tighter tolerance or the AD7864 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin.
PAGE 13
AD7864 CIRCUIT DESCRIPTION ANALOG INPUT Table 5. Ideal Input/Output Code Table for the AD7864-1 The AD7864 is offered in three models: the AD7864-1, where each input can be configured for ±10 V or a ±5 V input voltage range; the AD7864-3, which handles the input voltage range of ±2.5 V; and the AD7864-2, where each input can be configured to have a 0 V to +2.5 V or 0 V to +5 V input voltage range.
PAGE 14
AD7864 The designed code transitions take place midway between successive integer least significant bit values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, and so on). Least significant bit size is given by the formula 1 LSB = FSR/4096. Output coding is twos complement binary with 1 LSB = FSR/4096 = 5 V/4096 = 1.22 mV. The ideal input/ output transfer function for the AD7864-3 is shown in Table 7. Table 6.
PAGE 15
AD7864 SELECTING A CONVERSION SEQUENCE Any subset of the four channels, VIN1 to VIN4, can be selected for conversion. The selected channels are converted in ascending order. For example, if the channel selection includes VIN4, VIN1, and VIN3, the conversion sequence is VIN1, VIN3, and then VIN4. The conversion sequence selection can be made either by using the hardware channel select input pins (SL1 through SL4) or by programming the channel select register.
PAGE 16
AD7864 logic high). The pointer is incremented to point to the next register (next conversion result) when that conversion result is available. Thus, FRSTDATA in Figure 9 is shown as going low just prior to the second EOC pulse. Repeated read operations during a conversion continue to access the data at the current pointer location until the pointer is incremented at the end of that conversion. Note that FRSTDATA has an indeterminate logic state after initial power-up.
PAGE 17
AD7864 Successive read operations access the remaining conversion results in an ascending channel order. Each read operation increments the output data register pointer. The read operation that accesses the last conversion result causes the output data register pointer to be reset so that the next read operation accesses the first conversion result again. This is shown in Figure 10, wherein the fifth read after BUSY goes low accessing the result of the conversion on VIN1.
PAGE 18
AD7864 STANDBY MODE OPERATION 1.0 0.9 POWER-UP TIME (ms) 0.8 0.7 0.6 0.5 +105°C 0.4 +25°C 0.3 0.2 0.1 –40°C 0 0.0001 0.001 0.01 0.1 STANDBY TIME (Seconds) ACCESSING THE OUTPUT DATA REGISTERS There are four output data registers, one for each of the four possible conversion results from a conversion sequence. The result of the first conversion in a conversion sequence is placed in Register 1, the second result is placed in Register 2, and so forth.
PAGE 19
AD7864 When reading the output data registers after a conversion sequence, that is, when BUSY goes low, the register pointer is incremented on the rising edge of the RD signal, as shown in Figure 14. However, when reading the conversion results during the conversion sequence, the pointer is not incremented until a valid conversion result is in the register to be addressed. In this case, the pointer is incremented when the conversion has ended and the result has been transferred to the output data register.
PAGE 20
AD7864 OFFSET AND FULL-SCALE ADJUSTMENT Figure 15 shows a circuit that can be used to adjust the offset and full-scale errors on the AD7864 (VINxA on the AD7864-1 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7864 while the input voltage is 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of −2.
PAGE 21
AD7864 DYNAMIC SPECIFICATIONS graph is 72.6 dB. Note that the harmonics are taken into account when calculating the SNR. 0 –20 –30 –40 –60 –80 SNR = (6.02N + 1.76) dB (1) where N is the number of bits. Thus, for an ideal 12-bit converter, SNR = 74 dB. Figure 16 shows a histogram plot for 8192 conversions of a dc input using the AD7864 with a 5 V supply. The analog input was set at the center of a code.
PAGE 22
AD7864 2.5 terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). 0 AD7864-1 @ 25°C 5V SUPPLY SAMPLING AT 131072Hz INPUT FREQUENCY OF 48,928Hz AND 50,016Hz 4096 SAMPLES TAKEN –10 –20 –30 1.5 1.0 0 –0.5 –1.0 –1.5 –2.5 500 1000 1500 2000 2500 3000 3500 4000 ADC CODE Figure 21.
PAGE 23
AD7864 From Figure 22, the ENOB of the AD7864 at 1 MHz is approximately 11 bits. This is equivalent to 68 dB SNR. From Equation 3 70.2 dB = 20 × log10[1/(2 × π × 1 MHz × σ)] SNRTOTAL = SNRJITTER + SNRQUANT = 68 dB 68 dB = SNRJITTER + 72 dB (at 100 kHz) σ = 49 ps where σ is the rms jitter of the AD7864. SNRJITTER = 70.2 dB Rev.
PAGE 24
AD7864 MICROPROCESSOR INTERFACING AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102 INTERFACE requirements. The following instruction is used to read the conversion results from the AD7864: IN D,ADC where D is the data memory address and ADC is the AD7864 address. TMS320C5x Figure 23 shows an interface between the AD7864 and the ADSP-210x. The CONVST signal can be generated by the ADSP-210x or from some other external source.
PAGE 25
AD7864 Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three-phase drive currents into separate torque and flux components.
PAGE 26
AD7864 the different channels. The AD7864 has a maximum aperture delay matching of 4 ns. MULTIPLE AD7864S IN A SYSTEM Figure 27 shows a system where a number of AD7864s are configured to handle multiple input channels. This type of configuration is common in applications such as sonar and radar. The AD7864 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels.
PAGE 27
AD7864 OUTLINE DIMENSIONS 1.03 0.88 0.73 14.15 13.90 SQ 13.65 2.45 MAX 34 44 1.95 REF 1 33 PIN 1 SEATING PLANE 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 2.20 2.00 1.80 0.23 0.11 23 11 0.25 MIN 0.10 COPLANARITY 7° 0° 22 12 VIEW A VIEW A 0.80 BSC LEAD PITCH 0.45 0.30 LEAD WIDTH COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 041807-A ROTATED 90° CCW Figure 28.