Datasheet

AD7863
Rev. B | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1, 2
A, B Versions Unit Test Conditions/Comments
t
CONV
5.2 μs max Conversion time
t
ACQ
0.5 μs max Acquisition time
Parallel Interface
t
1
0 ns min
CS to RD setup time
t
2
0 ns min
CS to RD hold time
t
3
35 ns min
CONVST pulse width
t
4
45 ns min
RD pulse width
t
5
3
30 ns min
Data access time after falling edge of
RD
t
6
4
5 ns min
Bus relinquish time after rising edge of
RD
30 ns max
t
7
10 ns min Time between consecutive reads
t
8
400 ns min Quiet time
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
V
A1
V
A2
V
B1
V
B2
CONVST
BUSY
A0
CS
RD
DATA
t
CONV
= 5.2µs
06411-002
t
3
t
8
t
ACQ
t
1
t
4
t
2
t
5
t
6
t
7
Figure 2. Timing Diagram
TO OUTPUT
PIN
1.6mA
200µA
50pF
06411-003
Figure 3. Load Circuit for Access Time and Bus Relinquish Time