Datasheet

AD7858/AD7858L
REV. B
–25–
Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2 which is the SPI/QSPI interface mode. Here the SYNC
input is active low and may be pulsed or tied permanently low.
If SYNC is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, otherwise with a
pulsed SYNC input a continuous SCLK may be applied pro-
vided SYNC is low for only 16 SCLK cycles. In Figure 33 the
SYNC going low disables the three-state on the DOUT pin.
The first falling edge of the SCLK after the SYNC going low
clocks out the first leading zero on the DOUT pin. The DOUT
pin is three-stated again a time t
12
after the SYNC goes high.
With the DIN pin the data input has to be set up a time t
7
be-
fore the SCLK rising edge as the part samples the input data on
the SCLK rising edge in this case. If resetting the interface is
required, the SYNC must be taken high and then low.
t
11
t
12
16654321
t
10
t
8
t
6
t
9
t
8
t
6
t
3
t
5
THREE-STATE THREE-STATE
DB0DB10DB11DB12DB13DB14
DB15 DB14 DB13 DB12 DB11 DB10 DB0
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
POLARITY PIN LOGIC HIGH
t
3
= –0.4t
SCLK
MIN (NONCONTINUOUS SCLK) ⴞ0.4t
SCLK
ns MIN/MAX (CONTINUOUS SCLK),
t
6
= 75/115ns MAX (5V/3V), t
7
= 40/60ns MIN (5V/3V), t
8
= 20/30ns MIN (5V/3V),
t
11
= 30/50ns MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4t
SCLK
ns MIN/MAX
(CONTINUOUS SCLK) (5V/3V)
DB15
t
7
Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation
with DIN Input, DOUT Output, and
SYNC Input