Datasheet

AD7856
–5–REV. A
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 285 kHz, reading and writ-
ing must be performed during conversion as in Figure 3. At
least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of CONVST)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the CONVST signal, the conversion can be initiated in software
by writing to the control register.
t
CONVERT
= 3.5ms MAX, 5.25ms MAX FOR K VERSION
t
1
= 100ns MIN, t
4
= 30/50ns MAX A/K, t
7
= 30/40ns MIN A/K
DB15
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
CONVERT
1
5
616
DOUT (O/P) DB0
DB11
DIN (I/P)
DB15
DB0
THREE-
STATE
DB11
THREE-STATE
t
1
t
2
t
4
t
6
t
6
t
9
t
11
t
12
t
8
t
7
t
10
Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
DB15
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
CONVERT
1
5
616
DOUT (O/P) DB0
DB11
DIN (I/P)
DB15
DB0
THREE-
STATE
DB11
THREE-STATE
t
1
t
2
t
4
t
6
t
6
t
9
t
11
t
12
t
8
t
7
t
10
t
CONVERT
= 3.5ms MAX, 5.25ms MAX FOR K VERSION
t
1
= 100ns MIN, t
4
= 30/50ns MAX A/K, t
7
= 30/40ns MIN A/K
Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
TO OUTPUT
PIN
C
L
100pF
I
OL
1.6mA
200mA
+2.1V
I
OL
Figure 1. Load Circuit for Digital Output Timing
Specifications