Datasheet
–3–REV. A
AD7856
Parameter A Version
1
K Version
1
Units Test Conditions/Comments
POWER PERFORMANCE
AV
DD,
DV
DD
+4.75/+5.25 +4.75/+5.25 V min/max
I
DD
Normal Mode
5
17 17 mA max AV
DD
= DV
DD
= 4.75 V to 5.25 V. Typically 12 mA
Sleep Mode
6
With External Clock On 30 10 µA typ Full Power-Down. Power Management Bits in Con-
trol Register Set as PMGT1 = 1, PMGT0 = 0
400 500 µA typ Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off 5 5 µA max Typically 0.5 µA. Full Power-Down. Power Manage-
ment. Bits in Control Register Set as PMGT1 = 1,
PMGT0 = 0
200 200 µA typ Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
Normal Mode Power Dissipation 89.25 89.25 mW max V
DD
= 5.25 V. Typically 60 mW; SLEEP = V
DD
Sleep Mode Power Dissipation
With External Clock On 52.5 52.5 µW typ V
DD
= 5.25 V. SLEEP = 0 V
With External Clock Off 26.25 26.25 µW max V
DD
= 5.25 V. Typically 5.25 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.0375 × V
REF
/–0.0375 × V
REF
V max/min Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+1.01875 × V
REF
/–0.98125 × V
REF
V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature ranges as follows: A Version: –40°C to +105°C. K Version: 0°C to +105°C.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for CONVST, SLEEP, CAL and SYNC @ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
DD
. No load on the digital outputs.
Analog inputs @ AGND.
7
The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7856 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.0375 × V
REF
, and
the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
± 0.01875 × V
REF
).
This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.