Datasheet
AD7856
–19–REV. A
A combination of hardware and software selection can also be
used to achieve the desired effect.
Table VI.␣ Power Management Options
PMGT1 PMGT0 SLEEP
Bit Bit Pin Comment
0 0 0 Full Power-Down Between
Conversions (HW/SW)
0 0 1 Full Power-Up (HW/SW)
0 1 X Normal Operation
(Independent of the SLEEP
Pin)
1 0 X Full Power-Down (SW)
1 1 X Partial Power-Down Between
Conversions
NOTE
HW = Hardware Selection; SW = Software Selection.
POWER-UP TIMES
Using an External Reference
When the AD7856 is powered up, the part is powered up from
one of two conditions. First, when the power supplies are ini-
tially powered up and, secondly, when the part is powered up
from either a hardware or software power-down (see last section).
When AV
DD
and DV
DD
are powered up, the AD7856 should be
left idle for approximately 42 ms (6 MHz CLK) to allow for the
autocalibration if a 10 nF cap is placed on the CAL pin, (see
Calibration section). During power-up the functionality of the
SLEEP pin is disabled, i.e., the part will not power down until
the end of the calibration if SLEEP is tied logic low. The auto-
calibration on power-up can be disabled if the CAL pin is tied to
a logic high. If the autocalibration is disabled, then the user must
take into account the time required by the AD7856 to power-up
before a self-calibration is carried out. This power-up time is the
time taken for the AD7856 to power up when power is first
applied (300 µs) typ) or the time it takes the external reference
to settle to the 14-bit level–whichever is the longer.
AUTO POWER
DOWN AFTER
CONVERSION
AUTO CAL ON
POWER-UP
AV
DD
DV
DD
AIN(+)
AIN(–)
C
REF1
C
REF2
SLEEP
DIN
DOUT
SYNC
CONVST
AGND
DGND
CLKIN
SCLK
REF
IN
/REF
OUT
AD7856
ANALOG
SUPPLY
+5V
0.1mF
0.1mF10mF
0.1mF
0.01mF
MASTER CLOCK
INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.1mF
CAL
0.01mF
INTERNAL
REFERENCE
0V TO 2.5V
INPUT
4/6MHz OSCILLATOR
SERIAL CLOCK
INPUT
100kHz PULSE GENERATOR
OPTIONAL
EXTERNAL
REFERENCE
REF-192
SERIAL DATA INPUT
LOW POWER
mC/mP
CURRENT, I = 12mA TYP
Figure 21. Typical Low Power Circuit