Datasheet

AD7854/AD7854L
–4–
REV. B
Limit at T
MIN
, T
MAX
(A, B, S Versions)
Parameter 5 V 3 V Units Description
f
CLKIN
2
500 500 kHz min Master Clock Frequency
4 4 MHz max
1.8 1.8 MHz max L Version
t
1
3
100 100 ns min CONVST Pulsewidth
t
2
50 90 ns max CONVST to BUSY ↑ Propagation Delay
t
CONVERT
4.5 4.5 µs max Conversion Time = 18 t
CLKIN
10 10 µs max L Version 1.8 MHz CLKIN. Conversion Time = 18 t
CLKIN
t
3
15 15 ns min HBEN to RD Setup Time
t
4
5 5 ns min HBEN to RD Hold Time
t
5
0 0 ns min CS to RD to Setup Time
t
6
0 0 ns min CS to RD Hold Time
t
7
55 70 ns min RD Pulsewidth
t
8
4
50 50 ns max Data Access Time After RD
t
9
5
5 5 ns min Bus Relinquish Time After RD
40 40 ns max
t
10
60 70 ns min Minimum Time Between Reads
t
11
0 0 ns min HBEN to WR Setup Time
t
12
5 5 ns max HBEN to WR Hold Time
t
13
0 0 ns min CS to WR Setup Time
t
14
0 0 ns max CS to WR Hold Time
t
15
55 70 ns min WR Pulsewidth
t
16
10 10 ns min Data Setup Time Before WR
t
17
5 5 ns min Data Hold Time After WR
t
18
4
1/2 t
CLKIN
1/2 t
CLKIN
ns min New Data Valid Before Falling Edge of BUSY
t
19
50 70 ns min HBEN High Pulse Duration
t
20
50 70 ns min HBEN Low Pulse Duration
t
21
40 60 ns min Propagation Delay from HBEN Rising Edge to Data Valid
t
22
40 60 ns min Propagation Delay from HBEN Falling Edge to Data Valid
t
23
2.5 t
CLKIN
2.5 t
CLKIN
ns max CS↑ to BUSY ↑ in Calibration Sequence
t
CAL
6
31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013
t
CLKIN
)
t
CAL1
6
27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 t
CLKIN
)
t
CAL2
6
3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent
(13889 t
CLKIN
)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth applies (see Power-Down
section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
9
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
9
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7854 and 1.8 MHz for AD7854L;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)