Datasheet

Parameter A Version
1
B Version
1
S Version
1
Units Test Conditions/Comments
POWER REQUIREMENTS
AV
DD,
DV
DD
+3.0/+5.5 +3.0/+5.5 +3.0/+5.5 V min/max
I
DD
Normal Mode
5
5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA
(1.5 mA);
5.5 (1.8) 5.5 (1.8) 6 (1.8) mA max AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA
(1.5 mA).
Sleep Mode
6
With External Clock On 10 10 10 µA typ Full power-down. Power management bits in control
register set as PMGT1 = 1, PMGT0 = 0.
400 400 400 µA typ Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
With External Clock Off 5 5 5 µA max Typically 1 µA. Full power-down. Power management
bits in control register set as PMGT1 = 1,
PMGT0 = 0.
200 200 200 µA typ Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Normal Mode Power Dissipation 30 (10) 30 (10) 30 (10) mW max V
DD
= 5.5 V: Typically 25 mW (8)
20 (6.5) 20 (6.5) 20 (6.5) mW max V
DD
= 3.6 V: Typically 15 mW (5.4)
Sleep Mode Power Dissipation
With External Clock On 55 55 55 µW typ V
DD
= 5.5 V
36 36 36 µW typ V
DD
= 3.6 V
With External Clock Off 27.5 27.5 27.5 µW max V
DD
= 5.5 V: Typically 5.5 µW
18 18 18 µW max V
DD
= 3.6 V: Typically 3.6 µW
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.05 × V
REF
/–0.05 × V
REF
V max/min Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+0.025 × V
REF
/–0.025 × V
REF
V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature ranges as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2
Specifications apply after calibration.
3
Not production tested. Guaranteed by characterization at initial product release.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for CONVST @ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST @ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ±0.05 × V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
± 0.025 × V
REF
(unipolar mode) and V
REF
/2 ± 0.025 × V
REF
(bipolar mode)). This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD7854/AD7854L