Datasheet

AD7849
Rev. C | Page 5 of 20
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are no subject to test. V
REF+
= 5 V; V
DD
= 14.25 V to 15.75 V; V
SS
= −14.25 V to
−15.75 V; V
CC
= 4.75 V to 5.25 V; R
OFS
connected to 0 V.
Table 3.
Parameter A, B, C Versions Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Settling Time
1
7 μs typ To 0.006% FSR. V
OUT
loaded. V
REF−
= 0 V.
10 μs typ To 0.003% FSR. V
OUT
loaded. V
REF−
= −5 V.
Slew Rate 4 V/μs typ
Digital-to-Analog Glitch Impulse 250 nV-sec typ
DAC alternatively loaded with 00 … 00 and
111 … 11. V
OUT
loaded. LDAC permanently low.
BIN
/COMP set to 1. V
REF−
= −5 V.
150 nV-sec typ
LDAC
frequency = 100 kHz.
AC Feedthrough 1 mV p-p typ
V
REF−
= 0 V, V
REF+
= 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s. BIN
/COMP set to 0.
Digital Feedthrough 5 nV-sec typ
DAC alternatively loaded with all 1s and 0s.
SYNC high.
Output Noise Voltage Density, 1 kHz to 100 kHz 80 nV/√Hz typ
Measured at V
OUT
. V
REF+
= V
REF−
= 0 V.
BIN
/COMP set to 0.
1
LDAC
= 0. Settling time does not include deglitching time of 5 μs (typical).
TIMING CHARACTERISTICS
V
DD
= 14.25 V to 15.75 V; V
SS
= −14.25 V to −15.75 V; V
CC
= 4.75 V to 5.25 V; R
L
= 2 kΩ, C
L
= 200 pF. All specifications T
MIN
to T
MAX
,
unless otherwise noted. Guaranteed by characterization. All input signals are specified tr = tf = 5 ns (10% to 90% of 5 V and timed from a
voltage level of 1.6 V.
Table 4.
Parameter Limit at 25°C (All Versions) Limit at T
MIN
, T
MAX
(All Versions) Unit Test Conditions/Comments
t
1
1
200 200 ns min SCLK cycle time
t
2
50 50 ns min
SYNC
-to-SCLK setup time
t
3
70 70 ns min
SYNC
-to-SCLK hold time
t
4
10 10 ns min Data setup time
t
5
40 40 ns min Data hold time
t
6
2
80 80 ns max SCLK falling edge to SDO valid
t
7
80 80 ns min
LDAC
, CLR pulse width
t
r
30 30 μs max Digital input rise time
t
f
30 30 μs max Digital input fall time
1
SCLK mark/space ratio range is 40/60 to 60/40.
2
SDO load capacitance is 50 pF.