Datasheet

AD7846
Rev. G | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= +14.25 V to +15.75 V, V
SS
= −14.25 V to −15.75 V, V
CC
= +4.75 V to +5.25 V, unless otherwise noted.
Table 3.
Parameter
1
Limit at T
MIN
to T
MAX
(All Versions) Unit Test Conditions/Comments
t
1
0 ns min
R/W
to CS setup time
t
2
60 ns min
CS
pulse width (write cycle)
t
3
0 ns min
R/W
to CS hold time
t
4
60 ns min Data setup time
t
5
0 ns min Data hold time
t
6
2
120 ns max Data access time
t
7
3
10 ns min Bus relinquish time
60 ns max
t
8
0 ns min
CLR
setup time
t
9
70 ns min
CLR
pulse width
t
10
0 ns min
CLR
hold time
t
11
70 ns min
LDAC
pulse width
t
12
130 ns min
CS
pulse width (read cycle)
1
Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a
voltage level of 1.6 V.
2
t
6
is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6.
DB0
TO
DB15
5V
t
3
t
1
t
3
DATA VALIDDATA VALID
t
11
t
10
LDAC
CLR
CS
R/W
0V
5V
0V
5V
0V
5V
0V
5V
0V
t
10
t
8
t
9
t
6
t
1
t
8
t
9
t
4
t
5
t
7
t
12
t
2
0
8490-006
Figure 2. Timing Diagram
DBn
3kΩ
100pF
DGND
0
8490-002
Figure 3. Load Circuit for Access Time (t
6
)—High Z to V
OH
DBn
100pF
3kΩ
DGND
5
V
08490-003
Figure 4. Load Circuits for Bus Relinquish Time (t
6
)—High Z to V
OL
DBn
3kΩ
10pF
DGND
08490-004
Figure 5. Load Circuit for Access Time (t
7
)—High Z to V
OH
DBn
10pF
3kΩ
DGND
5
V
08490-005
Figure 6. Load Circuits for Bus Relinquish Time (t
7
)—High Z to V
OL