Datasheet

AD7846
Rev. G | Page 12 of 24
S1
V
REF+
V
REF–
DAC1
SEGMENT 1
SEGMENT 16
S3
S15
S17
S16
S14
S4
S2
DAC2
DAC3
12-BIT DAC
DB11 TO DB0
DB15 TO DB12 DB15 TO DB12
R
R
V
OUT
R
IN
A3
A2
A1
08490-021
Figure 21. Digital-to-Analog Conversion
OUTPUT STAGE
The output stage of the AD7846 is shown in Figure 22. It is capable
of driving a 2 kΩ/1000 pF load. It also has a resistor feedback
network that allows the user to configure it for gains of 1 or 2.
Table 6 shows the different output ranges that are possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 µs
after the leading edge of
LDAC
. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. Thus, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC
is tied permanently low, the deglitching is not in
operation. and show the outputs of the
AD7846 without and with the deglitcher.
Figure 13 Figure 14
C1
LDAC
V
OUT
R
IN
DAC3
ONE
SHOT
10kΩ
10kΩ
08490-022
Figure 22. Output Stage