Datasheet

AD7845
REV. B –7–
UNIPOLAR BINARY OPERATION
Figure 13 shows the AD7845 connected for unipolar binary
operation. When V
IN
is an ac signal, the circuit performs
2-quadrant multiplication. The code table for Figure 13 is given
in Table I.
Figure 13. Unipolar Binary Operation
Table I. Unipolar Binary Code Table for AD7845
Binary Number In
DAC Register Analog Output, V
OUT
MSB LSB
1111 1111 1111 –V
IN
4095
4096






1000 0000 0000 –V
IN
2048
4096






= –1/2 V
IN
0000 0000 0001 –V
IN
1
4096






0000 0000 0000 0 V
OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13
Zero Offset Adjustment
1. Load DAC with all 0s.
2. Trim R3 until V
OUT
= 0 V.
Gain Adjustment
1. Load DAC with all 1s.
2. Trim R1 so that V
OUT
= –V
IN
4095
4096
.
In fixed reference applications, full scale can also be adjusted by
omitting R1 and R2 and trimming the reference voltage magni-
tude. For high temperature applications, resistors and potenti-
ometers should have a low temperature coefficient.
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit for bipolar operation is shown in
Figure 14. Offset binary coding is used.
The offset specification of this circuit is determined by the
matching of internal resistors R
B
and R
C
and by the zero code
offset error of the device. Gain error may be adjusted by varying
the ratio of R1 and R2.
To use this circuit without trimming and keep within the gain
error specifications, resistors R1 and R2 should be ratio
matched to 0.01%.
The code table for Figure 14 is given in Table II.
Figure 14. Bipolar Offset Binary Operation
Table II. Bipolar Code Table for Offset Binary Circuit of
Figure 14
Binary Number In
DAC Register Analog Output, V
OUT
MSB LSB
1111 1111 1111 +V
IN
2047
2048






1000 0000 0001 +V
IN
1
2048






1000 0000 0000 0 V
0111 1111 1111 –V
IN
1
2048






0000 0000 0000 –V
IN
2048
2048






= –V
IN