Datasheet

–3–
AD7841
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
A & B
Parameter Versions Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 31 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
Slew Rate 0.7 V/µs typ
Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with V
REF
(+) = +5 V, V
REF
(–) = –5 V. DAC Latch
Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions
Channel-to-Channel Isolation 99 dB typ See Terminology
DAC-to-DAC Crosstalk 40 nV-s typ See Terminology
Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density
@ 1 kHz 200 nV/√Hz typ All 1s Loaded to DAC. V
REF
(+) = V
REF
(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1, 2
Parameter Limit at T
MIN,
T
MAX
Unit Description
t
1
15 ns min Address to WR Setup Time
t
2
0 ns min Address to WR Hold Time
t
3
50 ns min CS Pulsewidth Low
t
4
50 ns min WR Pulsewidth Low
t
5
0 ns min CS to WR Setup Time
t
6
0 ns min WR to CS Hold Time
t
7
20 ns min Data Setup Time
t
8
0 ns min Data Hold Time
t
9
31 µs typ Settling Time
t
10
300 ns max CLR Pulse Activation Time
t
11
50 ns min LDAC Pulsewidth Low
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t
1
t
2
t
5
t
6
t
3
t
4
t
7
t
8
t
9
t
10
t
11
LDAC
CLR
WR
CS
A0, A1, A2
DATA
V
OUT
V
OUT
Figure 1. Timing Diagram
(V
CC
= 5 V  5%; V
DD
= 15 V  10%; V
SS
= –15 V  10%; GND = DUTGND = 0 V)
REV. B