Datasheet

AD7841
–12–
GND
V
DD
8/10-BIT
DAC
GND
V
DD
8/10-BIT
DAC
LOGIC LEVEL
SHIFT
+5V
5V
SCLK
D IN
FSIN/CS
SCLK
D IN
FSIN/CS
0V TO +5V
0V TO 5V
V
REF
(+)AB
A0, A1, A2
V
OUT
A
V
OUT
A
V
OUT
B
V
OUT
B
V
REF
()AB
AD7841*
GND
DATA BUS
ADDR
DECODER
ADDR BUS
SDATA
SCLK
DATA BUS
CONTROLLER
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. Programmable Reference Generation for the AD7841
The AD8803 has an output voltage range of GND to V
DD
(0 V
to 5 V). To trim the V
REF
(+) input, the appropriate trim range
on the AD8803 DAC can be set using the V
REFL
and V
REFH
pins
allowing 8 bits of resolution between the two points. This will
allow the V
REF
(+) pin to be adjusted to remove gain errors.
To trim the V
REF
(–) voltage, some method of providing a trim
voltage in the required negative voltage range is required. Neither
the AD7804 or the AD8803 can provide this range in normal
operation as their output range is 0 V to 5 V. There are two
methods of producing this negative voltage. One method is to
provide a positive output voltage and then to level shift that ana-
log voltage to the required negative range. Alternatively these
DACs can be operated with supplies of 0 V and –5 V, with the
V
DD
pin connected to 0 V and the GND pin connected to –5 V.
Now these can be used to provide the negative reference volt-
ages for the V
REF
(–) inputs on the AD7841. However, the digital
signals driving the DACs need to be level-shifted from the 0 V
to +5 V range to the –5 V to 0 V range. Figure 13 shows a
typical application circuit to provide programmable reference
capabilities for the AD7841.
REV. B