Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) MQFP 44

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which may result from its use. No license is granted by implication or

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AD7841

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Octal 14-Bit, Parallel Input,

Voltage-Output DAC

FUNCTIONAL BLOCK DIAGRAM

DAC

REG

INPUT

REG

DAC E

AD7841

DB13

DB0

LDAC

DAC

REG

INPUT

REG

DAC

REG

INPUT

REG

DAC

REG

INPUT

REG

DAC

REG

INPUT

REG

DAC

REG

INPUT

REG

DAC

REG

INPUT

REG

DAC

REG

INPUT

REG

DAC D

DAC C

DAC F

DAC B

DAC A

DAC G

DAC H

REF

(+)

REF

(–)

DUTGND

OUT

DUTGND

REF

(–)

CDEF

REF

(+)

CDEF

REF

(–)

REF

(+)

GND

CLR

ADDRESS

DECODE

14 14

14 14 14

FEATURES

Eight 14-Bit DACs in One Package

Voltage Outputs

Offset Adjust for Each DAC Pair

Reference Range of 5 V

Maximum Output Voltage Range of 10 V

15 V  10% Operation

Clear Function to User-Defined Voltage

44-Lead MQFP Package

APPLICATIONS

Automatic Test Equipment

Process Control

General Purpose Instrumentation

GENERAL DESCRIPTION

The AD7841 contains eight 14-bit DACs on one monolithic

chip. It has output voltages with a full-scale range of ± 10 V

from reference voltages of ±5 V.

The AD7841 accepts 14-bit parallel loaded data from the exter-

nal bus into one of the input registers under the control of the

WR, CS, and DAC channel address pins, A0–A2.

The DAC outputs are updated on reception of new data into

the DAC registers. All the outputs may be updated simulta-

neously by taking the LDAC input low.

Each DAC output is buffered with a gain-of-two amplifier into

which an external DAC offset voltage can be inserted via the

DUTGNDx pins.

The AD7841 is available in a 44-lead MQFP package.

REV. B

Fax: 781/461-3113

Summary of content (13 pages)

PAGE 1
a Octal 14-Bit, Parallel Input, Voltage-Output DAC AD7841 GENERAL DESCRIPTION FEATURES Eight 14-Bit DACs in One Package Voltage Outputs Offset Adjust for Each DAC Pair Reference Range of 5 V Maximum Output Voltage Range of 10 V 15 V 10% Operation Clear Function to User-Defined Voltage 44-Lead MQFP Package The AD7841 contains eight 14-bit DACs on one monolithic chip. It has output voltages with a full-scale range of ± 10 V from reference voltages of ± 5 V.
PAGE 2
(VCC = 5 V 5%; VDD = 15 V 10%; VSS = –15 V 10%; GND = DUTGND = 1 L L A = TMIN to TMAX, unless otherwise noted) AD7841–SPECIFICATIONS 0 V; R = 5 k and C = 50 pF to GND, T Parameter A B Unit ACCURACY Resolution Relative Accuracy Differential Nonlinearity 14 ±4 –0.9/2 14 ±2 ±1 Bits LSB max LSB max Zero-Scale Error ±8 ±8 LSB max Full-Scale Error ±8 ±8 LSB max Gain Error Gain Temperature Coefficient 2 ±2 0.5 10 120 ±2 0.
PAGE 3
AD7841 AC PERFORMANCE CHARACTERISTICS (These characteristics are included for Design Guidance and are not subject to production testing.) Parameter A&B Versions Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 31 µs typ Full-Scale Change to ± 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s Slew Rate 0.7 Digital-to-Analog Glitch Impulse 230 V/µs typ nV-s typ Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk 99 40 0.
PAGE 4
AD7841 ABSOLUTE MAXIMUM RATINGS 1, 2 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C MQFP Package Power Dissipation . . . . . . . . . . . . . . . . . (TJ Max – TA)/θJA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W (TA = 25°C unless otherwise noted) VCC to GND3 . . . . . . . . . . . . . . –0.3 V, +7 V or VDD + 0.3 V (Whichever Is Lower) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VSS to GND . . . . . . . . . . . . . .
PAGE 5
AD7841 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DUTGND_AB 2, 44, 43, 41, 37, 35, 34, 32 3, 4 5, 38 6 7 VOUTA . . VOUTH Device Sense Ground for DACs A and B. VOUTA and VOUTB are referenced to the voltage applied to this pin. DAC Outputs. VREF(–)AB, VREF(+)AB VDD VSS LDAC 8, 9, 10 A2, A1, A0 11 12 CS WR 13 14 15–28 VCC GND DB0 . . DB12 29 CLR 30, 31 33 VREF(+)GH, VREF(–)GH DUTGND_GH 36 DUTGND_EF 39 40 42 VREF(+)CDEF VREF(–)CDEF DUTGND_CD REV.
PAGE 6
AD7841 TERMINOLOGY Relative Accuracy DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in Least Significant Bits.
PAGE 7
Typical Performance Characteristics– AD7841 1 2 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V TA = 25 C 0.5 0.25 0 –0.25 VDD = +15V VSS = –15V VREF(+) = +5V VREF(–) = –5V TA = 25 C –0.5 –1 –0.75 0 –1 2048 4096 6144 8192 10240 12288 14336 16384 0 0 –2 2048 4096 6144 8192 10240 12288 14336 16384 –1 –40 TPC 1. Typical INL Plot TPC 2.
PAGE 8
AD7841 When bipolar-zero and full-scale adjustment are not needed, R2 and R3 can be omitted. Pin 12 on the AD588 should be connected to Pin 11 and Pin 5 should be left floating. Unipolar Configuration Figure 2 shows the AD7841 in the unipolar binary circuit configuration. The VREF(+) input of the DAC is driven by the AD586, a 5 V reference. VREF(–) is tied to ground. Table II gives the code table for unipolar operation of the AD7841.
PAGE 9
AD7841 Power-On with CLR Low G1 The output stage of the AD7841 has been designed to allow output stability during power-on. If CLR is kept low during power-on, then just after power is applied to the AD7841, the situation is as depicted in Figure 5. G1, G4 and G6 are open while G2, G3 and G5 are closed. G6 DAC VOUT G3 G2 G4 R G1 R G5 14k G6 DAC VOUT G3 G2 Figure 7.
PAGE 10
AD7841 DUTGND Voltage Range CONTROLLER/ DSP PROCESSOR* During power-on, the VOUT pins of the AD7841 are connected to the relevant DUTGND pins via G5 and the 14 kΩ thin-film resistor. The DUTGND potential must obey the max ratings at all times. Thus, the voltage at DUTGND must always be within the range VSS – 0.3 V, VDD + 0.3 V.
PAGE 11
AD7841 The AD7841 should have ample supply bypassing located as close to the package as possible, ideally right up against the device. Figure 11 shows the recommended capacitor values of 10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF capacitors are the tantalum bead type. The 0.
PAGE 12
AD7841 The AD8803 has an output voltage range of GND to VDD (0 V to 5 V). To trim the VREF(+) input, the appropriate trim range on the AD8803 DAC can be set using the VREFL and VREFH pins allowing 8 bits of resolution between the two points. This will allow the VREF(+) pin to be adjusted to remove gain errors. provide a positive output voltage and then to level shift that analog voltage to the required negative range.
PAGE 13
AD7841 OUTLINE DIMENSIONS 1.03 0.88 0.73 14.15 13.90 SQ 13.65 2.45 MAX 34 44 1.95 REF 1 33 PIN 1 SEATING PLANE 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 2.20 2.00 1.80 0.23 0.11 23 11 0.25 MIN 0.10 COPLANARITY 7° 0° 22 12 VIEW A VIEW A 0.80 BSC LEAD PITCH 0.45 0.30 LEAD WIDTH COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 041807-A ROTATED 90° CCW Figure 14.