Datasheet

REV. C
–2–
AD7837/AD7847–SPECIFICATIONS
1
(V
DD
= +15 V  5%, V
SS
= –15 V  5%, AGNDA = AGNDB = DGND
= O V. V
REFA
= V
REFB
= +10 V, R
L
= 2 k, C
L
= 100 pF [V
OUT
connected to R
FB
AD7837]. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter A Version B Version S Version Units Test Conditions/Comments
STATIC PERFORMANCE
Resolution 12 12 12 Bits
Relative Accuracy
2
±1 ±1/2 ±1 LSB max
Differential Nonlinearity
2
±1 ±1 ±1 LSB max Guaranteed Monotonic
Zero Code Offset Error
2
@ +25°C ±2 ±2 ±2 mV max DAC Latch Loaded with All 0s
T
MIN
to T
MAX
±4 ±3 ±4 mV max Temperature Coefficient = ±5 µV/°C typ
Gain Error
2
@ +25°C ±4 ±2 ±4 LSB max DAC Latch Loaded with All 1s
T
MIN
to T
MAX
±5 ±3 ±5 LSB max Temperature Coefficient = ±2 ppm of
FSR/°C typ
REFERENCE INPUTS
V
REF
Input Resistance 8/13 8/13 8/13 kΩ min/max Typical Input Resistance = 10 kΩ
V
REFA
, V
REFB
Resistance Matching ±2 ±2 ±2 % max Typically ±0.25%
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 0.8 V max
Input Current ±1 ±1 ±1 µA max Digital Inputs at 0 V and V
DD
Input Capacitance
3
8 8 8 pF max
ANALOG OUTPUTS
DC Output Impedance 0.2 0.2 0.2 Ω typ
Short Circuit Current 11 11 11 mA typ V
OUT
Connected to AGND
POWER REQUIREMENTS
4
V
DD
Range 14.25/15.75 14.25/15.75 14.25/15.75 V min/max
V
SS
Range –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 V min/max
Power Supply Rejection
∆Gain/∆V
DD
±0.01 ±0.01 ±0.01 % per % max V
DD
= 15 V ± 5%, V
REF
= –10 V
∆Gain/∆V
SS
±0.01 ±0.01 ±0.01 % per % max V
SS
= –15 V ± 5%, V
REF
= +10 V
I
DD
8 8 8 mA max Outputs Unloaded. Inputs at Thresholds.
Typically 5 mA
I
SS
6 6 6 mA max Outputs Unloaded. Inputs at Thresholds.
Typically 3 mA
AC CHARACTERISTICS
2, 3
Voltage Output Settling Time 3 3 3 µs typ Settling Time to Within ±1/2 LSB of Final
555µs max Value. DAC Latch Alternately Loaded
with All 0s and All 1s
Slew Rate 11 11 11 V/µs typ
Digital-to-Analog Glitch Impulse 10 10 10 nV secs typ 1 LSB Change Around Major Carry
Channel-to-Channel Isolation
V
REFA
to V
OUTB
–95 –95 –95 dB typ V
REFA
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
V
REFB
to V
OUTA
–95 –95 –95 dB typ V
REFB
= 20 V p-p, 10 kHz Sine Wave.
DAC Latches Loaded with All 0s
Multiplying Feedthrough Error –90 –90 –90 dB typ V
REF
= 20 V p-p, 10 kHz Sine Wave.
DAC Latch Loaded with All 0s
Unity Gain Small Signal BW 750 750 750 kHz typ V
REF
= 100 mV p-p Sine Wave. DAC
Latch Loaded with All 1s
Full Power BW 175 175 175 kHz typ V
REF
= 20 V p-p Sine Wave. DAC
Latch Loaded with All 1s
Total Harmonic Distortion –88 –88 –88 dB typ V
REF
= 6 V rms, 1 kHz. DAC Latch
Loaded with All 1s
Digital Crosstalk 1 1 1 nV secs typ Code Transition from All 0s to All 1s and
Vice Versa
Output Noise Voltage @ +25°C See Typical Performance Graphs
(0.1 Hz to 10 Hz) 2 2 2 µV rms typ Amplifier Noise and Johnson Noise of R
FB
Digital Feedthrough 1 1 1 nV secs typ
NOTES
1
Temperature ranges are as follows: A, B Versions, –40°C to +85°C; S Version, –55°C to +125°C.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
The Devices are functional with V
DD
/V
SS
= ± 12 V (See typical performance graphs.).
Specifications subject to change without notice.