1 (V = +15 V 5%, V = –15 V 5%, AGNDA = AGNDB = DGND AD7837/AD7847–SPECIFICATIONS = O V. V = V = +10 V, R = 2 k , C = 100 pF [V connected to R AD7837]. All specifications T to T unless otherwise noted.
AD7837/AD7847 TIMING CHARACTERISTICS1, 2, 3 (VDD = +15 V 5%, VSS = –15 V 5%, AGNDA = AGNDB = DGND = O V) Parameter Limit at TMIN, TMAX (All Versions) Unit Conditions/Comments t1 t2 t3 t4 t5 t6 4 t7 4 t8 4 0 0 30 80 0 0 0 50 ns min ns min ns min ns min ns min ns min ns min ns min CS to WR Setup Time CS to WR Hold Time WR Pulsewidth Data Valid to WR Setup Time Data Valid to WR Hold Time Address to WR Setup Time Address to WR Hold Time LDAC Pulsewidth NOTES 1 All input signals are specified with
AD7837/AD7847 Channel-to-Channel Isolation TERMINOLOGY Relative Accuracy (Linearity) This is an ac error due to capacitive feedthrough from the VREF input on one DAC to VOUT on the other DAC. It is measured with the DAC latches loaded with all 0s. Relative accuracy, or endpoint linearity, is a measure of the maximum deviation of the DAC transfer function from a straight line passing through the endpoints.
AD7837/AD7847 AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Pin Mnemonic Description 11 12 13 14 15 16 17 18 19 10 11 12 13 CSA CSB VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB VREFB DGND DB11 WR 14–24 DB10–DB0 Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low. Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low. Reference Input Voltage for DAC A. This may be an ac or dc signal.
AD7837/AD7847–Typical Performance Graphs 0.6 25 10 VDD = +15V VSS = –15V 0.4 0.2 20 0 VDD = +15V VSS = –15V VREF = +20Vp–p –20 DAC CODE = 111...111 –30 104 105 15 10 5 106 0 10 107 FREQUENCY – Hz 0.5 0.3 INL 0.2 0.1 DNL 0 11 13 15 VDD /VSS – Volts 17 Figure 4. Linearity vs. Power Supply –0.6 0.6 0.4 –0.2 DAC CODE = 111...111 –0.4 100 1k LOAD RESISTANCE – DAC B 0 –0.6 10k 2048 CODE 0 4095 Figure 3.
AD7837/AD7847 CIRCUIT INFORMATION D/A SECTION Table I. AD7847 Truth Table A simplified circuit diagram for one of the D/A converters and output amplifier is shown in Figure 10. A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A-C. The remaining 10 bits drive the switches (S0–S9) in a standard R-2R ladder configuration. Each of the switches A–C steers 1/4 of the total reference current with the remaining 1/4 passing through the R-2R section.
AD7837/AD7847 UNIPOLAR BINARY OPERATION A0/A1 ADDRESS DATA t6 Figure 15 shows DAC A on the AD7837/AD7847 connected for unipolar binary operation. Similar connections apply for DAC B. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. The code table for this circuit is shown in Table III. Note that on the AD7847 the feedback resistor RFB is internally connected to VOUT. t7 CS t1 t2 t3 WR t4 VDD t5 VDD AD7837 AD7847 VALID DATA DATA VREFA t8 DGND VSS AGNDA Figure 14.
AD7837/AD7847 BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) APPLICATIONS Figure 16 shows the AD7837/AD7847 connected for bipolar operation. The coding is offset binary as shown in Table IV. When VIN is an ac signal, the circuit performs 4-quadrant multiplication. To maintain the gain error specifications, resistors R1, R2 and R3 should be ratio matched to 0.01%. Note that on the AD7847 the feedback resistor RFB is internally connected to VOUT.
AD7837/AD7847 ANALOG PANNING CIRCUIT 0.6 TOTAL POWER VARIATION – dB In audio applications it is often necessary to digitally “pan” or split a single signal source into a two-channel signal while maintaining the total power delivered to both channels constant. This may be done very simply by feeding the signal into the VREF input of both DACs. The digital codes are chosen such that the code applied to DAC B is the two's complement of that applied to DAC A.
AD7837/AD7847 MICROPROCESSOR INTERFACING–AD7837 ADDRESS BUS 8086 ALE ADDRESS DECODE 16 BIT LATCH CSA CSB AD7847* WR WR DB11 DB0 AD15 AD0 ADDRESS/DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. AD7847 to 8086 Interface AD7847–MC68000 Interface Figure 21 shows an interface between the AD7847 and the MC68000. Once again a single MOVE instruction loads the 12-bit word into the selected DAC latch. CSA and CSB are AND-gated to provide a DTACK signal when either DAC latch is selected.
AD7837/AD7847 AD7837–6502/6809 Interface A15 C01007a–0–8/00 (rev. C) Figure 25 shows an interface between the AD7837 and the 6502 or 6809 microprocessor. For the 6502 microprocessor, the φ2 clock is used to generate the WR, while for the 6809 the E signal is used. ADDRESS BUS A0 ADDRESS DECODE 6502/6809 LDAC EN R/W A0 A1 CS AD7837* 2 OR E WR DB7 DB0 D7 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25.
