Datasheet
AD7836
–9–
REV. A
Power-On with CLR Low
The output stage of the AD7836 has been designed to allow
output stability during power-on. If CLR is kept low during
power-on, then just after power is applied to the AD7836, the
situation is as depicted in Figure 14. G
1
, G
4
and G
6
are open
while G
2
, G
3
and G
5
are closed.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 14. Output Stage with V
DD
< 10 V
V
OUT
is kept within a few hundred millivolts of DUTGND via
G
5
and a 6kΩ resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The out-
put amplifier is connected as a unity gain buffer via G
3
, and the
DUTGND voltage is applied to the buffer input via G
2
. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 14 until
the voltage at V
DD
and V
SS
reaches approximately ±10 V. By
now the output amplifier has enough headroom to handle sig-
nals at its input and has also had time to settle. The internal
power-on circuitry opens G
3
and G
5
and closes G
4
and G
6
. This
situation is shown in Figure 15. Now the output amplifier is
configured in its noise gain configuration via G
4
and G
6
. The
DUTGND voltage is still connected to the noninverting input
via G2 and this voltage appears at V
OUT
.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 15. Output Stage with V
DD
> 10 V and
CLR
Low
V
OUT
has been disconnected from the DUTGND pin by the
opening of G
5
but will track the voltage present at DUTGND
via the configuration shown in Figure 15.
When CLR is taken back high, the output stage is configured as
shown in Figure 16. The internal control logic closes G
1
and
opens G
2
. The output amplifier is connected in a noninverting
gain of two configuration. The voltage that appears on the Vout
pins is determined by the data present in the DAC registers. To
set all output voltages to the same known state, a write to
DATA REG E with the SEL pin high allows all DAC registers
to be updated with the same data.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 16. Output Stage After
CLR
Is Taken High
Power-On with CLR High
If CLR is high on the application of power to the device, the
output stages of the AD7836 are configured as in Figure 17
while V
DD
/V
SS
are less than ±10 V. G
1
is closed and G
2
is open
thereby connecting the output of the DAC to the input of its
output amplifier. G
3
and G
5
are closed while G
4
and G
6
are
open thus connecting the output amplifier as a unity gain
buffer. V
OUT
is connected to DUTGND via G
5
through a 6 kΩ
resistor until V
DD
and V
SS
reach approximately ±10 V.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 17. Output Stage Powering Up with
CLR
High
While V
DD
/V
SS
<
±
10 V
When the supplies reach ±10 V, the internal power on circuitry
opens G
3
and G
5
and closes G
4
and G
6
configuring the output
stage as shown in Figure 18.
DAC
G
1
G
3
V
OUT
6k
G
6
G
4
G
5
G
2
DUTGND
R
R
Figure 18. Output Stage Powering Up with
CLR
High
When V
DD
/V
SS
>
±
10 V