Datasheet

AD7834/AD7835
Rev. D | Page 6 of 28
TIMING SPECIFICATIONS
V
CC
= 5 V ± 5%; V
DD
= 11.4 V to 15.75 V; V
SS
= −11.4 V to −15.75 V; AGND = DGND = 0 V
1
.
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
AD7834-SPECIFIC
t
1
2
100 ns min SCLK cycle time
t
2
2
50 ns min SCLK low
t
3
2
30 ns min SCLK high time
t
4
30 ns min
FSYNC, PAEN setup time
t
5
40 ns min
FSYNC, PAEN hold time
t
6
30 ns min Data setup time
t
7
10 ns min Data hold time
t
8
0 ns min
LDAC to FSYNC setup time
t
9
40 ns min
LDAC to FSYNC hold time
t
21
20 ns min Delay between write operations
AD7835-SPECIFIC
t
11
15 ns min
A0, A1, A2,
BYSHF to CS setup time
t
12
15 ns min
A0, A1, A2,
BYSHF to CS hold time
t
13
0 ns min
CS to WR setup time
t
14
0 ns min
CS to WR hold time
t
15
40 ns min
WR pulse width
t
16
40 ns min Data setup time
t
17
10 ns min Data hold time
t
18
0 ns min
LDAC to CS setup time
t
19
0 ns min
CS to LDAC setup time
t
20
0 ns min
LDAC to CS hold time
GENERAL
t
10
40 ns min
LDAC, CLR pulse width
1
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of 5 V) and time from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
t
1
t
3
t
10
t
21
t
9
t
4
LDAC
(SIMULTANEOUS
UPDATE)
LDAC
(PER-CHANNEL
UPDATE
)
1ST
CLK
2ND
CLK
24TH
CLK
t
5
t
8
t
2
D23 D22
t
7
t
6
D1
D0
SCLK
DIN
MSB LSB
FSYNC
01006-003
t
12
t
14
t
17
t
16
t
15
t
10
t
18
t
19
t
11
t
13
A0 A1 A2
CS
WR
DB0 TO DB13
LDAC
(SIMULTANEOUS
UPDATE)
LDAC
(PER-CHANNEL
UPDATE)
t
20
BYSHF
01006-004
Figure 3. AD7834 Timing Diagram Figure 4. AD7835 Timing Diagram