Datasheet

AD7834/AD7835
Rev. D | Page 22 of 28
INTERFACING THE AD7835—8-BIT INTERFACE
When writing to the DACs, the lower eight bits must be written
first, followed by the upper six bits. The upper six bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a
Figure 32 shows an 8-bit interface between the AD7835 and
a generic 8-bit microcontroller/DSP processor. Pin D13 to
Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the
processor are connected to Pin D7 to Pin D0 of the AD7835.
CS
signal. They
are also decoded in conjunction with lines A3 to A0 to provide
an
BYSHF
is driven by the A0 line of the processor. This maps the
DAC upper bits and lower bits into adjacent bytes in the proces-
sor address space.
Table 14 shows the truth table for addressing
the DACs in the AD7835. For example, if the base address for the
DACs in the processor address space is decoded by the upper
address bits to location HC000, then the upper and lower bits of
the first DAC are at locations HC000 and HC001, respectively.
ADDRESS
DECODE
D7
D0
A2
A1
A0
R/W
DATABUS
UPPER BITS OF
ADDRESS BUS
A3
AD7835
1
D7
D0
CS
LDAC
A2
A1
A0
BYSHF
D13
D8
DGND
WR
1
ADDITIONAL PINS OMITTED FOR CLARITY
MICROCONTROLLER/
DSP
PROCESSOR
1
01006-032
Figure 32. AD7835 8-Bit Interface
LDAC LDAC
signal. Alternatively, can be driven by an exter-
nal timing circuit or, if it is acceptable to allow the DAC output
to go to an intermediate value between 8-bit writes,
LDAC
can
be tied low.
Table 14. DAC Channel Decoding, 8-Bit Interface
Processor Address Lines
A3 A2 A1 A0 DAC Selected
x X X 0 Upper 6 bits of all DACs
1 X X 1 Lower 8 bits of all DACs
0 0 0 0 Upper 6 bits, DAC 1
0 0 0 1 Lower 8 bits, DAC 1
0 0 1 0 Upper 6 bits, DAC 2
0 0 1 1 Lower 8 bits, DAC 2
0 1 0 0 Upper 6 bits, DAC 3
0 1 0 1 Lower 8 bits, DAC 3
0 1 1 0 Upper 6 bits, DAC 4
0 1 1 1 Lower 8-bits, DAC 4