Datasheet

AD7834/AD7835
Rev. D | Page 17 of 28
CONTROLLED POWER-ON OF THE OUTPUT STAGE
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG 01006-023
A block diagram of the output stage of the AD7834/AD7835 is
shown in
Figure 21. It is capable of driving a load of 10 kΩ in
parallel with 200 pF. G
1
to G
6
are transmission gates used to
control the power-on voltage present at V
OUT
. G
1
and G
2
are also
used in conjunction with the
CLR
input to set V
OUT
to the user-
defined voltage present at the DSG pin.
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
01006-021
Figure 23. Output Stage with V
DD
> 10 V and
CLR
Low
V
OUT
is disconnected from the DSG pin by the opening of G
5
but tracks the voltage present at DSG via the unity gain buffer.
Figure 21. Block Diagram of AD7834/AD7835 Output Stage
POWER-ON WITH CLR LOW, LDAC HIGH
The output stage of the AD7834/AD7835 is designed to allow
output stability during power-on. If
CLR
is kept low during
power-on, and power is applied to the part, G
1
, G
4
, and G
6
are
open while G
2
, G
3
, and G
5
are closed (see Figure 22).
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
01006-022
Figure 22. Output Stage with V
DD
< 10 V
V
OUT
is kept within a few hundred millivolts of DSG via G
5
and R. R is a thin-film resistor between DSG and V
OUT
. The
output amplifier is connected as a unity gain buffer via G
3
, and
the DSG voltage is applied to the buffer input via G
2
. The
amplifier output is thus at the same voltage as the DSG pin. The
output stage remains configured as in
Figure 22 until the
voltage at V
DD
and V
SS
reaches approximately ±10 V. At this
point, the output amplifier has enough headroom to handle
signals at its input and has also had time to settle. The internal
power-on circuitry opens G
3
and G
5
and closes G
4
and G
6
(see
Figure 23). As a result, the output amplifier is connected in
unity gain mode via G
4
and G
6
. The DSG voltage is still applied
to the noninverting input via G
2
. This voltage appears at V
OUT
.
POWER-ON WITH LDAC LOW, CLR HIGH
LDAC
In many applications of the AD7834/AD7835, is kept
continuously low, updating the DAC after each valid data
transfer. If
LDAC
is low when power is applied, G
1
is closed and
G
2
is open, connecting the output of the DAC to the input of the
output amplifier. G
3
and G
5
are closed and G
4
and G
6
are open,
connecting the amplifier as a unity gain buffer, as before. V
OUT
is
connected to DSG via G
5
and R (a thin-film resistance between
DSG and V
OUT
) until V
DD
and V
SS
reach approximately ±10 V.
Then, the internal power-on circuitry opens G
3
and G
5
and
closes G
4
and G
6
. This is the situation shown in Figure 24. At
this point, V
OUT
is at the same voltage as the DAC output.
DAC
G
1
G
3
V
OUT
R
G
6
G
4
G
5
G
2
DSG
01006-024
LDAC
Figure 24. Output Stage with
Low
LOADING THE DAC AND USING THE CLR INPUT
LDAC
When goes low, it closes G
1
and opens G
2
as in Figure 24.
The voltage at V
OUT
now follows the voltage present at the out-
put of the DAC. The output stage remains connected in this
manner until a
CLR
signal is applied. Then, the situation reverts
(see
Figure 23). Once again, V
OUT
remains at the same voltage as
DSG until
LDAC
goes low. This reconnects the DAC output to
the unity gain buffer.