Datasheet

AD7834/AD7835
Rev. D | Page 15 of 28
D23 D22 D21
D20 D19
D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.
CONTROL BIT TO USE/IGNORE
FOLLOWING 23 BITS OF INFORMATION
CHANNEL ADDRESS MSB, D1
CHANNEL ADDRESS LSB, D2
PACKAGE ADDRESS MSB, PA4
PACKAGE ADDRESS, PA3
PACKAGE ADDRESS, PA2
PACKAGE ADDRESS, PA1
PACKAGE ADDRESS LSB, PA0
LSB, DB0
SECOND LSB, DB1
THIRD LSB, DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
THIRD MSB, DB11
SECOND MSB, DB12
MSB, DB13
SECOND LEADING ZERO
FIRST LEADING ZERO
01006-018
Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834
When 14-bit transfers are being used, the DAC output voltages,
V
OUT
1 to V
OUT
4, can be updated to reflect new data in the DAC
input registers in one of two ways. The first method normally
keeps
LDAC
high and only pulses
LDAC
low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties
LDAC
low, and channel updating occurs on a per channel basis after
new data is loaded to an input register.
To avoid the DAC output going to an intermediate value during
a 2-byte transfer,
LDAC
should not be tied low permanently but
should be held high until the two bytes are written to the input
register. When the selected input register has been loaded with
the two bytes,
LDAC
should then be pulsed low to update the
DAC latch and, consequently, perform the digital-to-analog
conversion.
In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications,
LDAC
can be tied low, thus using one less
control line.
The actual DAC input register that is being written to is deter-
mined by the logic levels present on the device address lines, as
shown in
Tabl e 11.
Table 11. AD7835—Address Line Truth Table
A2 A1 A0 DAC Selected
0 0 0 DAC 1
0 0 1 DAC 2
0 1 0 DAC 3
0 1 1 DAC 4
1 X X All DACs selected
UNIPOLAR CONFIGURATION
Figure 19 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The V
REF
(+) input of the DAC is driven by
the
gives the code table for unipolar operation of the AD7834/
AD7835.
+15V +5V
V
OUT
(0V TO 5V)
V
CC
2
6
8
5
4
SIGNAL
GND
C1
1nF
AGND
DGND
V
DD
V
OUT
V
REF
(+)
V
REF
(–)
V
SS
–15V
1
ADDITIONAL PINS OMITTED FOR CLARITY
R1
10kΩ
AD7834/
AD7835
1
AD586
SIGNAL
GND
01006-019
Figure 19. Unipolar 5 V Operation
Offset and gain can be adjusted in Figure 19 as follows:
• To adjust offset, disconnect the V
REF
(−) input from 0 V,
load the DAC with all 0s, and adjust the V
REF
(−) voltage
until V
OUT
= 0 V.
• To adjust gain, load the AD7834/AD7835 with all 1s and
adjust R1 until V
OUT
= 5 V(16383/16384) = 4.999695 V.
Many circuits do not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the
AD586 can be
left open circuit, and Pin 2 (V
REF
(−)) of the AD7834/AD7835 is
tied to 0 V.
Table 12. Code Table for Unipolar Operation
1, 2
Binary Number in DAC Latch
MSB
AD586, a 5 V reference. V
REF
(−) is tied to ground. Table 12
LSB Analog Output (V
OUT
)
V
REF
(16383/16384) V 11 1111 1111 1111
V
REF
(8192/16384) V 10 0000 0000 0000
V
REF
(8191/16384) V 01 1111 1111 1111
00 0000 0000 0001 V
REF
(1/16384) V
00 0000 0000 0000 0 V
1
V
REF
= V
REF
(+); VREF(−) = 0 V for unipolar operation.
2
For V
REF
(+) = 5 V, 1 LSB = 5 V/2
14
= 5 V/16384 = 305 μV.