Datasheet

AD7822/AD7825/AD7829
Rev. C | Page 11 of 28
A suggestion is to tie
CONVST
to V
DD
or DGND through a pull-up
or pull-down resistor. A rising edge on the
CONVST
pin causes
the AD7829 to fully power up, while a rising edge on the
PD
pin
causes the AD7822 and AD7825 to fully power up. For applica-
tions where power consumption is of concern, the automatic
power-down at the end of a conversion should be used to improve
power performance (see the
Power vs. Throughput section).
SUPPLY
4
.5V TO 5.5
V
10µF 0.1µF
V
DD
V
REF
V
MID
V
IN1
1.25V TO
3.75V INPUT
V
IN2
4
V
IN4
(V
IN8
5
)
AGND
DB0 TO DB7
EOC
RD
CS
CONVST
A0
1
A1
1
A2
2
PD
3
PARALLEL
INTERFACE
µC/µP
AD7822/
AD7825/
AD7829
DGND
2.5V
AD780
01321-009
1
A0, A1 AD7825/AD7829
2
A2 AD7829
3
PD AD7822/AD7825
4
V
IN2
TO V
IN4
AD7825/AD7829
5
V
IN5
TO V
IN8
AD7829
Figure 9. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7822/AD7825/AD7829 is straight
binary. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size =
V
REF
/256 (V
DD
= 5 V) or the LSB size = (0.8 V
REF
)/256 (V
DD
=
3 V). The ideal transfer characteristic for the AD7822/AD7825/
AD7829 is shown in
Figure 10.
11111111
111...110
111...000
10000000
000...111
000...010
00000000
(V
DD
= 5V)
1LSB = V
REF
/256
(V
DD
= 3V)
1LSB = 0.8V
REF
/256
000...001
ADC CODE
1LSB
V
MID
(V
DD
= 5V) V
MID
– 1.25V
(V
DD
= 3V) V
MID
– 1V
V
MID
+ 1.25V – 1LSB
V
MID
+ 1V – 1LSB
ANALOG INPUT VOLTAGE
0
1321-010
Figure 10. Transfer Characteristic
ANALOG INPUT
The AD7822 has a single input channel, and the AD7825 and
AD7829 have four and eight input channels, respectively. Each
input channel has an input span of 2.5 V or 2.0 V, depending on
the supply voltage (V
DD
). This input span is automatically set up
by an on-chip V
DD
detector circuit. A 5 V operation of the ADCs
is detected when V
DD
exceeds 4.1 V, and a 3 V operation is
detected when V
DD
falls below 3.8 V. This circuit also possesses
a degree of glitch rejection; for example, a glitch from 5.5 V to
2.7 V up to 60 ns wide does not trip the V
DD
detector.
The V
MID
pin is used to center this input span anywhere in the
range of AGND to V
DD
. If no input voltage is applied to V
MID
,
the default input range is AGND to 2.0 V (V
DD
= 3 V ± 10%),
that is, centered about 1.0 V; or AGND to 2.5 V (V
D
D = 5 V ±
10%), that is, centered about 1.25 V. When using the default
input range, the V
MID
pin can be left unconnected, or in some
cases, it can be decoupled to AGND with a 0.1 μF capacitor.
If, however, an external V
MID
is applied, the analog input range
is from V
MID
− 1.0 V to V
MID
+ 1.0 V (V
DD
= 3 V ± 10%), or
from V
MID
− 1.25 V to V
MID
+ 1.25 V (V
DD
= 5 V ± 10%).
The range of values of V
MID
that can be applied depends on the
value of V
DD
. For V
DD
= 3 V ± 10%, the range of values that can
be applied to V
MID
is from 1.0 V to V
DD
− 1.0 V and from 1.25 V to
V
DD
− 1.25 V when V
DD
= 5 V ± 10%. Table 5 shows the relevant
ranges of V
MID
and the input span for various values of V
DD
.
Figure 11 illustrates the input signal range available with various
values of V
MID
.
Table 5.
V
DD
V
MID
Internal
V
MID
Ext
Max
V
IN
Span
V
MID
Ext
Min
V
IN
Span Unit
5.5 1.25 4.25 3.0 to 5.5 1.25 0 to 2.5 V
5.0 1.25 3.75 2.5 to 5.0 1.25 0 to 2.5 V
4.5 1.25 3.25 2.0 to 4.5 1.25 0 to 2.5 V
3.3 1.00 2.3 1.3 to 3.3 1.00 0 to 2.0 V
3.0 1.00 2.0 1.0 to 3.0 1.00 0 to 2.0 V
2.7 1.00 1.7 0.7 to 2.7 1.00 0 to 2.0 V