Datasheet

AD7824/AD7828
REV. F
–3–
TIMING CHARACTERISTICS
1
(V
DD
= 5 V; V
REF
(+) = 5 V; V
REF
(–) = GND = 0 V, unless otherwise noted.)
Limit at 25ⴗC Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (All Grades) (K, L, B, C Grades) (T, U Grades) Unit Conditions/Comments
t
CSS
00 0 ns min CS to RD Setup Time
t
CSH
00 0 ns min CS to RD Hold Time
t
AS
00 0 ns min Multiplexer Address Setup Time
t
AH
30 35 40 ns min Multiplexer Address Hold Time
t
RDY
2
40 60 60 ns max CS to RDY Delay. Pull-Up
Resistor 5 kΩ.
t
CRD
2.0 2.4 2.8 µs max Conversion Time, Mode 0
t
ACC1
3
85 110 120 ns max Data Access Time after RD
t
ACC2
3
50 60 70 ns max Data Access Time after INT, Mode 0
t
lNTH
2
40 65 70 ns typ RD to INT Delay
75 100 100 ns max
t
DH
4
60 70 70 ns max Data Hold Time
t
P
500 500 600 ns min Delay Time between Conversions
t
RD
60 80 80 ns min Read Pulsewidth, Mode 1
600 500 400 ns max
NOTES
1
Sample tested at 25°C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
3k⍀ 100pF
DGND
a. High-Z to V
OH
DBN
3k⍀
100pF
DGND
5V
b. High-Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
DBN
3k⍀ 10pF
DGND
a. V
OH
to High-Z
DBN
3k⍀
10pF
DGND
5V
b. V
OL
to High-Z
Figure 2. Load Circuits for Data Hold Time Test