Datasheet

AD7821
REV. B
–3–
TIMING CHARACTERISTICS
1
(V
DD
= +5 V ⴞ 5%, V
SS
= 0 V or –5 V ⴞ 5%; Unipolar or Bipolar Input Range)
Limit at Limit at
Limit at +25ⴗCT
MIN
, T
MAX
T
MIN
, T
MAX
Parameter (All Versions) (K, B Versions) (T Version) Unit Conditions/Comments
t
CSS
000ns min CS to RD/WR Setup Time
t
CSH
000ns min CS to RD/WR Hold Time
t
RDY
2
70 85 100 ns max CS to RDY Delay. Pull-Up
Resistor 5 kΩ
t
CRD
700 875 975 ns max Conversion Time (RD Mode)
t
ACC0
3
Data Access Time (RD Mode)
t
CRD
+ 25 t
CRD
+ 30 t
CRD
+ 35 ns max C
L
= 20 pF
t
CRD
+ 50 t
CRD
+ 65 t
CRD
+ 75 ns max C
L
= 100 pF
t
INTH
2
50 – – ns typ RD to INT Delay (RD Mode)
80 85 90 ns max
t
DH
4
15 15 15 ns min Data Hold Time
60 70 80 ns max
t
P
350 425 500 ns min Delay Time Between Conversions
t
WR
250 325 400 ns min Write Pulsewidth
10 10 10 µs max
t
RD
250 350 450 ns min Delay Time between WR and RD Pulses
t
READ1
160 205 240 ns min RD Pulsewidth (WR-RD Mode, see Figure 12b)
Determined by t
ACC1
t
ACC1
3
Data Access Time (WR-RD Mode, see Figure 12b)
160 205 240 ns max C
L
= 20 pF
185 235 275 ns max C
L
= 100 pF
t
RI
150 185 220 ns max RD to INT Delay
t
INTL
2
380 – – ns typ WR to INT Delay
500 610 700 ns max
t
READ2
65 75 85 ns min RD Pulsewidth (WR-RD Mode, see Figure 12a)
Determined by t
ACC2
Data Access Time (WR-RD Mode, see Figure 12a)
t
ACC2
3
65 75 85 ns max C
L
= 20 pF
90 110 130 ns max C
L
= 100 pF
t
IHWR
2
80 100 120 ns max WR to INT Delay (Stand-Alone Operation)
t
ID
3
Data Access Time after INT
(Stand-Alone Operation)
30 35 40 ns max C
L
= 20 pF
45 60 70 ns max C
L
= 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
a. High Z to V
OH
b. High Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
a. V
OH
to High Z b. V
OL
to High Z
Figure 2. Load Circuits for Data Hold Time Test
ORDERING GUIDE
Total
Temperature Unadjusted Package
Model
1
Range Error (LSB) Option
2
AD7821KN –40°C to +85°C ±1 max N-20
AD7821KP –40°C to +85°C ±1 max P-20A
AD7821KR –40°C to +85°C ±1 max RW-20
AD7821BQ –40°C to +85°C ±1 max Q-20
AD7821TQ –55°C to +125°C ±1 max Q-20
AD7821TE –55°C to +125°C ±1 max E-20A
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.