Datasheet

REV. B
AD7819
–9–
PARALLEL INTERFACE
The parallel interface of the AD7819 is eight bits wide. The out-
put data buffers are activated when both CS and RD are logic
low. At this point the contents of the data register are placed on
the 8-bit data bus. Figure 15 shows the timing diagram for the par-
allel port. The Parallel Interface of the AD7819 is reset when
BUSY goes logic high. Care must be taken to ensure that a read
operation does not occur while BUSY is high. Data read from
the AD7819 while BUSY is high will be invalid. For optimum
performance the read operation should end at least 100 ns (t
8
)
prior to the falling edge of the next CONVST.
8 MSBs
t
1
t
2
t
3
t
POWER-UP
EXT CONVST
INT CONVST
BUSY
CS/RD
DB7–DB0
Figure 13. Mode 1 Operation
8 MSBs
t
1
t
3
EXT CONVST
INT CONVST
BUSY
CS/RD
DB7–DB0
t
POWER-UP
Figure 14. Mode 2 Operation
8 MSBs
CONVST
BUSY
CS
DB7–DB0
t
2
t
3
t
1
t
4
t
6
t
7
t
5
t
8
RD
Figure 15. Parallel Port Timing