Datasheet

AD7804/AD7805/AD7808/AD7809
–5–REV. A
AD7805/AD7809 TIMING CHARACTERISTICS
1
(V
DD
= 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference
= Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter All Versions Unit Description
t
1
25 ns min Mode Valid to Write Setup Time
t
2
4.5 ns min Mode Valid to Write Hold Time
t
3
25 ns min Address Valid to Write Setup Time
t
4
4.5 ns min Address Valid to Write Hold Time
t
5
25 ns min Data Setup Time
t
6
4.5 ns min Data Hold Time
t
6A
6 ns min LDAC Valid to Write Hold Time
t
7
40 ns min Chip Select to Write Setup Time
t
8
0 ns min Chip Select to Write Hold Time
t
9
40 ns min Write Pulsewidth
t
10
100 ns min Time Between Successive Writes
t
11
40 ns min LDAC, CLR Pulsewidth
t
12
100 ns min Write to LDAC Setup Time
NOTE
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
MODE
CS
WR
DATA
LDAC
2
CLR
LDAC
1
t
1
t
2
t
3
t
4
t
7
t
8
t
9
t
5
t
6
t
10
t
11
t
12
t
11
1
TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
t
6A
A0, A1, A2
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write