Datasheet

AD7804/AD7805/AD7808/AD7809
REV. A–4–
(V
DD
= 3.3 V ⴞ 10% to 5 V ⴞ 10%; AGND = DGND = 0 V; Reference =
Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter All Versions Units Description
t
1
100 ns min CLKIN Cycle Time
t
2
40 ns min CLKIN High Time
t
3
40 ns min CLKIN Low Time
t
4
30 ns min FSIN Setup Time
t
5
30 ns min Data Setup Time
t
6
5 ns min Data Hold Time
t
6A
6 ns min LDAC Hold Time
t
7
90 ns max FSIN Hold Time
20 ns min
t
8
40 ns min LDAC, CLR Pulsewidth
t
9
100 ns min LDAC Setup Time
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
CLKIN(I)
FSIN(I)
SDIN(I) DB15
t
2
t
3
t
7
t
8
CLR
LDAC
1
t
5
t
6A
t
1
t
9
t
8
t
4
t
5
t
6
DB0
1
TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.
LDAC
2
Figure 1. Timing Diagram for AD7804 and AD7808
AD7804/AD7808 TIMING CHARACTERISTICS
1