Datasheet
AD7804/AD7805/AD7808/AD7809
–23–REV. A
AD7805/AD7809–ADSP-2101 Interface
Figure 38 shows a parallel interface between the AD7805/AD7809
and the ADSP-2101/ADSP-2103 digital signal processor.
Fast interface timing allows the AD7805/AD7809 interface
directly to the DSP. In this interface an external timer is used to
update the DACs.
DATA BUS
A0 A1
CS
LDAC
WR
DMD0
DMD15
ADSP-2101*/
ADSP-2103*
TIMER
MODE
ADDR
DECODE
ADDRESS BUS
DMA0
DMA14
DMS
EN
WR
DB0
DB9
**ADDITIONAL PINS OMITTED FOR CLARITY
**A2 CONTAINED ON THE AD7809 ONLY
AD7805*/
AD7809
A2**
Figure 38. AD7805/AD7809–ADSP-2101/ADSP-2103
Interface
Data is loaded to the AD7805/AD7809 input register using the
following instruction:
DM(DAC) = MR0,
MR0 = ADSP-2101 MR0 Register.
DAC = Decoded DAC Address.
AD7805/AD7809–TMS32020 Interface
Figure 39 shows a parallel interface between the AD7805/AD7809
and the TMS32020 processor.
ADDR
DECODE
DATA BUS
ADDRESS BUS
A0 A1
CS
DB0
DB9
LDAC
A0
A15
IS
EN
D0
D15
TMS32020
WR
STRB
R/W
**ADDITIONAL PINS OMITTED FOR CLARITY
**A2 CONTAINED ON THE AD7809 ONLY
AD7805*/
AD7809
A2**
Figure 39. AD7805/AD7809–TMS32020 Interface
Again fast interface timing allows the AD7805/AD7809 inter-
face directly to the processor. Data is loaded to the AD7805/
AD7809 input latch using the following instruction:
OUT DAC, D.
DAC = Decoded DAC Address.
D = Data Memory Address.
Certain applications may require that the updating of the DAC
latch be controlled by the microprocessor rather than the exter-
nal timer. One option as shown in the TMS32020 interface is to
decode the LDAC from the address bus so that a write opera-
tion to the DAC latch (at a separate address to the input latch)
updates the output.
AD7805/AD7809–8051/8088 Interface
Figure 40 shows a parallel interface between the AD7805/
AD7809 and the 8051/8088 processors.
ADDRESS/DATA BUS
OCTAL
LATCH
MODE
WR
ALE
8051/8088
**ADDITIONAL PINS OMITTED FOR CLARITY
**A2 CONTAINED ON THE AD7809 ONLY
ADDR
DECODE
ADDRESS BUS
A0 A1
CS
AD7805*/
AD7809
A8
A15
PSEN OR DEN EN
LDAC
WR
AD7
AD0
A2**
DB0
DB9
Figure 40. AD7805/AD7809–8051/8088 Interface