Datasheet

–2–
REV. 0
AD7801–SPECIFICATIONS
(V
DD
= +2.7 V to +5.5 V, Internal Reference; C
L
= 100 pF, R
L
= 10 kV to V
DD
and GND.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter B Versions
1
Units Conditions/Comments
STATIC PERFORMANCE
Resolution 8 Bits
Relative Accuracy
2
±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Zero-Code Error @ +25°C 3 LSB typ All Zeros Loaded to DAC Register
Full-Scale Error –0.75 LSB typ All Ones Loaded to DAC Register
Zero-Code Error Drift 100 µV/°C typ
Gain Error
3
±1 % FSR typ
DAC REFERENCE INPUT
REFIN Input Range 1 to V
DD
/2 V min/V max
REFIN Input Impedance 10 M typ
OUTPUT CHARACTERISTICS
Output Voltage Range 0 to V
DD
V min/V max
Output Voltage Settling Time 2 µs max Typically 1.2 µs
Slew Rate 7.5 V/µs typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry
Digital Feedthrough 0.2 nV-s typ
DC Output Impedance 40 typ
Short Circuit Current 14 mA typ
Power Supply Rejection Ratio
4
0.0003 %/% max V
DD
= ±10%
LOGIC INPUTS
Input Current ±10 µA max
V
INL
, Input Low Voltage 0.8 V max V
DD
= +5 V
V
INL
, Input Low Voltage 0.6 V max V
DD
= +3 V
V
INH
, Input High Voltage 2.4 V min V
DD
= +5 V
V
INH
, Input High Voltage 2.1 V min V
DD
= +3 V
Pin Capacitance 7 pF max
POWER REQUIREMENTS
V
DD
2.7/5.5 V min/V max
I
DD
(Normal Mode) DAC Active and Excluding Load Current
V
DD
= 3.3 V V
IH
= V
DD
and V
IL
= GND
@ 25°C 1.55 mA max See Figure 6
T
MIN
to T
MAX
1.75 mA max
V
DD
= 5.5 V
@ 25°C 2.35 mA max
T
MIN
to T
MAX
2.5 mA max
I
DD
(Power-Down)
@ 25°C1µA max V
IH
= V
DD
and V
IL
= GND
T
MIN
to T
MAX
2 µA max See Figure 18
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +105°C
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
Figure 1. Timing Diagram for Parallel Data Write
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
CS
WR
D7-D0
LDAC
CLR