Datasheet

AD7794/AD7795
Rev. D | Page 26 of 36
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7794/AD7795 are low power ADCs that incorporate a
∑-Δ modulator, buffer, reference, in-amp, and on-chip digital
filtering, which are intended for the measurement of wide
dynamic range, low frequency signals (such as those in pressure
transducers), weigh scales, and temperature measurement
applications.
Each part has six differential inputs that can be buffered or
unbuffered. The devices operate with an internal 1.17 V refer-
ence or by using an external reference.
Figure 12 shows the
basic connections required to operate the parts.
The output rate of the AD7794/AD7795 (f
ADC
) is user pro-
grammable. The allowable update rates, along with the
corresponding settling times, are listed in
Table 19 for chop
enabled. With chop disabled, the allowable update rates remain
unchanged, but the settling time equals 1/f
ADC
. Normal mode
rejection is the major function of the digital filter. Simultaneous
50 Hz and 60 Hz rejection is optimized when the update rate
equals 16.7 Hz or less, as notches are placed at both 50 Hz and
60 Hz with these update rates (see
Figure 14).
The AD7794/AD7795 use slightly different filter types,
depending on the output update rate, so that the rejection of
quantization noise and device noise is optimized. When the
update rate is 4.17 Hz to 12.5 Hz, a Sinc3 filter along with an
averaging filter is used. When the update rate is 16.7 Hz to
39 Hz, a modified Sinc3 filter is used. This filter gives
simultaneous 50 Hz/60 Hz rejection when the update rate
equals 16.7 Hz. A Sinc4 filter is used when the update rate is
50 Hz to 242 Hz. Finally, an integrate-only filter is used when
the update rate equals 470 Hz. Figure 13 to Figure 16 show the
frequency response of the different filter types for some of the
update rates when chop is enabled. In this mode, the settling
time equals twice the update rate. Figure 17 to Figure 20 show
the filter response with chop disabled.
04854-012
DOUT/RD
Y
DIN
SCLK
CS
DV
DD
SERIAL
INTERFACE
AND
LOGIC
CONTROL
Σ-Δ
ADC
AD7794/AD7795
AIN1(+)
REFIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
AIN3(+)
AIN3(–)
REFIN2(+)
IOUT1
REFIN1(–)
IN-AMP
V
DD
GND
MUX
PSW
GND
INTERNAL
CLOCK
CLK
GND AV
DD
V
DD
IN+
IN–
OUT– OUT+
IN+
IN–
OUT– OUT+
R
CM
V
DD
REFIN2(–)
BUF
Figure 12. Basic Connection Diagram