Datasheet

AD7794/AD7795
Rev. D | Page 19 of 36
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit read/write register that is used to
select the operating mode, the update rate, and the clock source.
Table 17 outlines the bit designations for the mode register.
MR0 through MR15 indicate the bit locations with MR
denoting that the bits are in the mode register. MR15 is the first
bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit. Any write to the setup
register resets the modulator and filter, and sets the
RDY
bit.
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8
MD2(0) MD1(0) MD0(0) PSW(0) 0(0) 0(0) AMP-CM(0) 0(0)
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
CLK1(0) CLK0(0) 0(0) CHOP-DIS(0) FS3(1) FS2(0) FS1(1) FS0(0)
Table 17. Mode Register Bit Designations
Bit No. Mnemonic Description
MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operating mode of the AD7794/AD7795 (see Table 18).
MR12 PSW
Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can sink
up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode,
the power switch is opened.
MR11 to MR10 0 These bits must be programmed with a Logic 0 for correct operation.
MR9 AMP-CM
Instrumentation Amplifier Common-Mode Bit. This bit is used in conjunction with the CHOP-DIS bit. With
chop disabled, the user can operate with a wider range of common-mode voltages when AMP-CM is
cleared. However, the dc common-mode rejection degrades. With AMP-CM set, the span for the common-
mode voltage is reduced (see the Specifications section). However, the dc common-mode rejection is
significantly better.
MR8 0 This bit must be programmed with a Logic 0 for correct operation.
MR7 to MR6 CLK1 to CLK0
These bits are used to select the clock source for the AD7794/AD7795. Either the on-chip 64 kHz clock can
be used or an external clock can be used. The ability to use an external clock allows several AD7794/AD7795
devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock
drives the AD7794/AD7795.
CLK1 CLK0 ADC Clock Source
0 0 Internal 64 kHz clock. Internal clock is not available at the CLK pin.
0 1 Internal 64 kHz clock. This clock is made available at the CLK pin.
1 0
External 64 kHz. The external clock can have a 45:55 duty cycle (see the
Specifications section for the external clock).
1 1 External clock. The external clock is divided by 2 within the AD7794/AD7795.
MR5 0 This bit must be programmed with a Logic 0 for correct operation.
MR4 CHOP-DIS
This bit is used to enable or disable chop. On power-up or following a reset, CHOP-DIS is cleared so chop is
enabled. When CHOP-DIS is set, chop is disabled. This bit is used in conjunction with the AMP-CM bit.
When chop is disabled, the AMP-CM bit should be set. This limits the common-mode voltage that can be
used by the ADC, but the dc common-mode rejection does not degrade.
MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 19).