6-Channel, Low Noise, Low Power, 24-/16-Bit ∑-Δ ADC with On-Chip In-Amp and Reference AD7794/AD7795 FEATURES Industrial process control Instrumentation Blood analysis Smart transmitters Liquid/gas chromatography 6-digit DVM Up to 23 effective bits RMS noise: 40 nV @ 4.17 Hz, 85 nV @ 16.7 Hz Current: 400 μA typical Power-down: 1 μA maximum Low noise, programmable gain, instrumentation amp Band gap reference with 4 ppm/°C drift typical Update rate: 4.
Powered by TCPDF (www.tcpdf.
AD7794/AD7795 TABLE OF CONTENTS Features .............................................................................................. 1 Full-Scale Register...................................................................... 25 Applications....................................................................................... 1 ADC Circuit Information.............................................................. 26 General Description ..................................................................
AD7794/AD7795 SPECIFICATIONS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 CHOP ENABLED Output Update Rate No Missing Codes 2 AD7794 AD7795 Resolution RMS Noise and Update Rates Integral Nonlinearity Offset Error 3 Offset Error Drift vs. Temperature 4 Full-Scale Error3, 5 Gain Drift vs.
AD7794/AD7795 Parameter 1 Common-Mode Rejection AD7794B/AD7795B @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 AD7794C @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 CHOP DISABLED Output Update Rate No Missing Codes2 AD7794 AD7795 Resolution RMS Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature4 Full-Scale Error3, 5 Gain Drift vs.
AD7794/AD7795 Parameter 1 Normal Mode Rejection2, 6 Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common-Mode Rejection AD7794B/AD7795B @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 AD7794C @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 CHOP ENABLED or DISABLED REFERENCE INPUT Internal Reference Internal Reference Initial Accuracy Internal Reference Drift2 Power Supply Rejection External Reference External REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Aver
AD7794/AD7795 Parameter 1 BIAS VOLTAGE GENERATOR VBIAS VBIAS Generator Start-Up Time TEMPERATURE SENSOR Accuracy Sensitivity LOW-SIDE POWER SWITCH RON Allowable Current2 DIGITAL OUTPUTS (P1 and P2) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 INTERNAL/EXTERNAL CLOCK Internal Clock Frequency2 Duty Cycle External Clock Frequency Duty Cycle LOGIC INPUTS CS2 VINL, Input Low Voltage VINH, Input High Voltage SCLK (Schmitt-Triggered Input), CLK, and DIN2 AD7
AD7794/AD7795 Parameter 1 LOGIC OUTPUT (INCLUDING CLK) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD to GND DVDD to GND Power Supply Currents IDD Current IDD (Power-Down Mode) AD7794/AD7795 Unit Test Conditions/Comments DVDD − 0.
AD7794/AD7795 TIMING CHARACTERISTICS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2.
AD7794/AD7795 TIMING DIAGRAMS CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 04854-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev.
AD7794/AD7795 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND DVDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND AIN/Digital Input Current Operating Temperature Range B Grade C Grade Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +7 V −0.
AD7794/AD7795 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 24 DIN CLK 2 23 DOUT/RDY CS 3 NC 4 AIN6(+)/P1 5 AD7794/ AD7795 21 AVDD 20 GND 19 PSW TOP VIEW AIN1(+) 7 (Not to Scale) 18 AIN4(–)/REFIN2(–) AIN1(–) 8 17 AIN4(+)/REFIN2(+) AIN2(+) 9 16 AIN5(–)/IOUT1 AIN2(–) 10 15 AIN5(+)/IOUT2 AIN3(+) 11 14 REFIN1(–) AIN3(–) 12 13 REFIN1(+) NC = NO CONNECT 04854-005 AIN6(–)/P2 6 22 DVDD Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No.
AD7794/AD7795 Pin No. 18 Mnemonic AIN4(−)/REFIN2(−) 19 20 21 22 PSW GND AVDD DVDD 23 DOUT/RDY 24 DIN Description Analog Input/Negative Reference Input. AIN4(−) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere between GND and AVDD − 0.1 V. Low-Side Power Switch to GND. Ground Reference Point. Supply Voltage, 2.7 V to 5.25 V. Serial Interface Supply Voltage, 2.
AD7794/AD7795 RMS NOISE AND RESOLUTION SPECIFICATIONS The AD7794/AD7795 can be operated with chop enabled or chop disabled, allowing the ADC to be optimized for switching time or drift performance. With chop enabled, the settling time is two times the conversion time. However, the offset is continuously removed by the ADC leading to low offset and low offset drift. With chop disabled, the allowable update rates are the same as in chop enable mode. However, the settling time now equals the conversion time.
AD7794/AD7795 Internal Reference Table 8 shows the AD7794/AD7795 rms noise for some of the update rates and gain settings. The numbers given are for the bipolar input range with the internal 1.17 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 9 and Table 10 show the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets.
AD7794/AD7795 CHOP DISABLED With chop disabled, the switching time or settling time is reduced by a factor of two. However, periodic offset calibrations may now be required to remove offset and offset drift. When chop is disabled, the AMP-CM bit in the mode register should be set to 1. This limits the allowable common-mode voltage that can be used. However, the common-mode rejection degrades if the bit is not set.
AD7794/AD7795 14 8388750 12 8388700 10 8388650 8388600 8 6 8388550 4 8388500 2 8388450 0 200 400 600 800 04854-009 OCCURRENCE 8388800 04854-006 CODE READ TYPICAL PERFORMANCE CHARACTERISTICS 0 8388068 8388100 1000 8388150 8388200 8388250 8388300 8388350 8388396 CODE READING NUMBER Figure 6. Typical Noise Plot for the AD7794 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz, Chop Enabled) Figure 9.
AD7794/AD7795 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described in the following sections. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER RS2, RS1, RS0 = 0, 0, 0 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register.
AD7794/AD7795 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7795)/0x88 (AD7794) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. SR7 RDY(1) SR6 ERR(0) SR5 NOXREF(0) SR4 0(0) Table 16 outlines the bit designations for the status register.
AD7794/AD7795 MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A The mode register is a 16-bit read/write register that is used to select the operating mode, the update rate, and the clock source. denoting that the bits are in the mode register. MR15 is the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit.
AD7794/AD7795 Table 18. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied.
AD7794/AD7795 Table 19. Update Rates Available (Chop Enabled) 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fADC (Hz) x 470 242 123 62 50 39 33.2 19.6 16.7 16.7 12.5 10 8.33 6.25 4.
AD7794/AD7795 CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 The configuration register is a 16-bit read/write register that is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel. Table 20 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations. CON denotes that the bits are in the configuration register.
AD7794/AD7795 Bit No. CON5 Mnemonic REF_DET CON4 BUF CON3 to CON0 CH3 to CH0 Description Enables the reference detect function. When set, the NOXREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V. When cleared, the reference detect function is disabled. Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device.
AD7794/AD7795 DATA REGISTER IO REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(AD7795), 0x000000 (AD7794) RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 The IO register is an 8-bit read/write register that is used to enable the excitation currents and select the value of the excitation currents. The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set.
AD7794/AD7795 OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7795), 0x800000 (AD7794)) RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7795), 0x5XXX00 (AD7794) The offset register is a 16-bit register on the AD7795 and a 24-bit register on the AD7794. The offset register holds the offset calibration coefficient for the ADC and its power-on reset value is 0x8000/0x800000, for the AD7794/AD7795, respectively. The AD7794/AD7795 each have four offset registers.
AD7794/AD7795 ADC CIRCUIT INFORMATION 50 Hz and 60 Hz rejection is optimized when the update rate equals 16.7 Hz or less, as notches are placed at both 50 Hz and 60 Hz with these update rates (see Figure 14).
AD7794/AD7795 0 0 –10 –20 –20 (dB) (dB) –40 –30 –60 –40 –80 0 20 40 60 80 –60 120 100 04854-020 04854-017 –100 –50 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Filter Response with Update Rate = 4.17 Hz (Chop Enabled) Figure 16.
AD7794/AD7795 to transfer data into the on-chip registers, while DOUT/RDY is used for accessing data from the on-chip registers. SCLK is the serial clock input for the devices, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin also operates as a data ready signal; the line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete.
AD7794/AD7795 CS DIN 0x08 0x200A 0x58 DATA 04854-014 DOUT/RDY SCLK Figure 21. Single Conversion CS 0x58 0x58 DIN DATA DATA 04854-015 DOUT/RDY SCLK Figure 22. Continuous Conversion CS 0x5C DIN DATA DATA DATA 04854-016 DOUT/RDY SCLK Figure 23. Continuous Read Rev.
AD7794/AD7795 Single Conversion Mode Continuous Read In single conversion mode, the AD7794/AD7795 are placed in shutdown mode between conversions. When a single conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the mode register, the AD7794/AD7795 power up, perform a single conversion, and then return to shutdown mode. The on-chip oscillator requires 1 ms to power up. A conversion requires a time period of 2 × tADC. DOUT/RDY goes low to indicate the completion of a conversion.
AD7794/AD7795 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL INSTRUMENTATION AMPLIFIER The AD7794/AD7795 have six differential analog input channels. These are connected to the on-chip buffer amplifier when the devices are operated in buffered mode. When in unbuffered mode, the channels connect directly to the modulator. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier.
AD7794/AD7795 DATA OUTPUT CODING EXCITATION CURRENTS When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a miscalled voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111.
AD7794/AD7795 input also drives the reference voltage for the parts, the effect of the low frequency noise in the excitation source is removed, because the application is ratiometric. If the AD7794/AD7795 are used in nonratiometric applications, a low noise reference should be used. Recommended 2.5 V reference voltage sources for the AD7794/AD7795 include the ADR381 and ADR391, which are low noise, low power references. Also, note that the reference inputs provide a high impedance, dynamic load.
AD7794/AD7795 one conversion cycle when chop is disabled. For higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled, and two conversion cycles when chop is disabled. DOUT/RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the fullscale register of the selected channel.
AD7794/AD7795 APPLICATIONS INFORMATION The AD7794/AD7795 offer low cost, high resolution analog-todigital functions. Because the analog-to-digital function is provided by a ∑-Δ architecture, it makes the parts more immune to noisy environments, making them ideal for use in sensor measurement, and industrial and process control applications. A second advantage of using the AD7794/AD7795 in transducerbased applications is that the low-side power switch can be fully utilized in low power applications.
AD7794/AD7795 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 25.
