Datasheet

Data Sheet AD7791
Rev. A | Page 13 of 20
Table 12. Update Rates
FS2 FS1 FS0 f
ADC
(Hz) f3dB (Hz) RMS Noise (µV) Rejection
0 0 0 120 28 40 25 dB @ 60 Hz
0 0 1 100 24 25 25 dB @ 50 Hz
0 1 0 33.3 8 3.36
0 1 1 20 4.7 1.6 80 dB @ 60 Hz
1 0 0 16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting)
1 0 1 16.7 4 1.5 80 dB @ 50 Hz
1 1 0 13.3 3.2 1.2
1 1 1 9.5 2.3 1.1 67 dB @ 50/60 Hz
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the
RDY
bit/pin is set.