Datasheet

AD7790 Data Sheet
Rev. A | Page 12 of 20
Bit Location Bit Name Description
MR2 0 This bit must be programmed with a Logic 0 for correct operation.
MR1 BUF
Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in un-
buffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered
mode, allowing the user to place source impedances on the front end without contributing gain errors
to the system.
MR0 0 This bit must be programmed with a Logic 0 for correct operation.
Table 10. Operating Modes
MD1 MD0 Mode
0 0
Continuous Conversion Mode (De-
fault)
0 1 Reserved
1 0 Single Conversion Mode
1 1 Power-Down Mode
Table 11. Analog Input Ranges
G1 G0 Range
AD7790 LSB Size with V
REF
= +2.5 V
(µV)
0 0 ±V
REF
76.3
0 1 ±V
REF
/2 38.14
1 0 ±V
REF
/4 19.07
1 1 ±V
REF
/8 9.54
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output
word rate. Table 12 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in
the filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0
0(0) 0(0) CDIV1(0) CDIV0(0) 0(0) FS2(1) FS1(0) FS0(0)
Table 12. Filter Register Bit Designatins
Bit Location Bit Name Description
FR7–FR6 0 These bits must be programmed with a Logic 0 for correct operation.
FR5–FR4
CLKDIV1
CDIV0
These bits are used to operate the AD7790 in the lower power modes. The clock is internally divided and
the power is reduced.
00 Normal Mode
01 Clock Divided by 2
10 Clock Divided by 4
11 Clock Divided by 8
FR3 0 This bit must be programmed with a Logic 0 for correct operation.
FR2–FR0 FS2–FS0
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and
noise. The noise is the same for all gain settings. See Table 13 for the allowable update rates in full power
mode. In the low power modes, the update rates will be reduced. (See Reduced Current Modes.)
Table 13. Update Rates
FS2 FS1 FS0 f
ADC
(Hz) f3dB (Hz) RMS Noise (µV) Rejection
0 0 0 120 28 40 25 dB @ 60 Hz
0 0 1 100 24 25 25 dB @ 50 Hz
0 1 0 33.3 8 3.36
0 1 1 20 4.7 1.6 80 dB @ 60 Hz
1 0 0 16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting)
1 0 1 16.7 4 1.5 80 dB @ 50 Hz
1 1 0 13.3 3.2 1.2
1 1 1 9.5 2.3 1.1 62 dB @ 50/60 Hz
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x0000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the
RDY
bit/pin is set.